XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 29

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Port Signals
Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.
Table 15
block SelectRAM+ memory.
Table 15:
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time refer-
enced to the CLK pin.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the mem-
ory cells.
Write Enable—WE[A|B]
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the con-
tents of the memory cells referenced by the address bus
reflect on the data out bus.
Reset—RST[A|B]
The reset pin forces the data output bus latches to zero syn-
chronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
Address Bus—ADDR[A|B]<#:0>
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in
DS025-2 (v2.1) July 17, 2002
Width
16
1
2
4
8
describes the depth and width aspect ratios for the
Table
R
Block SelectRAM+ Port Aspect Ratios
15.
Depth
4096
2048
1024
Table
512
256
15.
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
ADDR Bus
DATA<15:0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
Data Bus
DATA<0>
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration option.
Address Mapping
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port. The physical RAM location addressed for a particular
width are described in the following formula (of interest only
when the two ports use different aspect ratios).
Table 16
width.
Table 16:
Creating Larger RAM Structures
The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing
delays. This achieves wider or deeper RAM structures with
a smaller timing penalty than when using normal routing
channels.
Location Constraints
Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC proper-
ties to transfer easily from array to array.
The LOC properties use the following form.
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Width
Port
16
1
2
4
8
Start = ((ADDR
End = ADDR
LOC = RAMB4_R#C#
shows low order address mapping for each port
4095...
2047...
1023...
511...
255...
Port Address Mapping
port
1
5
07
port
1
4
* Width
03
+1) * Width
1
3
06
1
2
01
Addresses
port
1
1
05
Table
1
0
Port
02
0
9
port
04
15.
0
8
00
) –1
0
7
03
0
6
01
0
5
02
Module 2 of 4
0
4
00
0
3
01
0
2
00
0
1
00
25
0
0