XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 40

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The following list details variations of the IOBUF symbol.
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When the IOBUF symbol used supports an I/O standard
that requires a differential amplifier input, the IOBUF auto-
matically configures with a differential amplifier input buffer.
The low-voltage I/O standards with a differential amplifier
input require an external reference voltage input V
Module 2 of 4
36
IOBUF
IOBUF_S_2
IOBUF_S_4
IOBUF_S_6
IOBUF_S_8
IOBUF_S_12
IOBUF_S_16
IOBUF_S_24
IOBUF_F_2
IOBUF_F_4
IOBUF_F_6
IOBUF_F_8
IOBUF_F_12
IOBUF_F_16
IOBUF_F_24
IOBUF_LVCMOS2
IOBUF_PCI33_3
IOBUF_PCI66_3
IOBUF_GTL
IOBUF_GTLP
IOBUF_HSTL_I
IOBUF_HSTL_III
IOBUF_HSTL_IV
IOBUF_SSTL3_I
IOBUF_SSTL3_II
IOBUF_SSTL2_I
IOBUF_SSTL2_II
IOBUF_CTT
IOBUF_AGP
IOBUF_LVCMOS18
IOBUF_LVDS
IOBUF_LVPECL
Figure 42: Input/Output Buffer Symbol (IOBUF)
T
O
I
IOBUF
x133_06_111699
IO
REF
.
www.xilinx.com
1-800-255-7778
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V
on page 33
Within each bank approximately one of every six I/O pins is
automatically configured as a V
ferential amplifier input signal within a given V
same external source must drive all I/O pins configured as a
V
IOBUF placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V
Additional restrictions on the Virtex-E SelectI/O IOBUF
placement require that within a given V
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require V
The LOC property can specify a location for the IOBUF.
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, acti-
vate the delay element with the DELAY=TRUE property.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the IOBUF (PUL-
LUP, PULLDOWN, or KEEPER).
SelectI/O Properties
Access to some of the SelectI/O features (for example, loca-
tion constraints, input delay, output drive strength, and slew
rate) is available through properties associated with these
features.
Input Delay Properties
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to over-
ride this default.
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to pro-
vide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.
REF
input.
CCO
for a representation of the Virtex-E I/O banks.
can be placed within the same V
REF
banks internally. See
REF
DS025-2 (v2.1) July 17, 2002
input. After placing a dif-
CCO
CCO
REF
bank each
banks.
CCO
Figure 38
bank, the
bank.
R