XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 22

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The corresponding timing characteristics are listed in
Table
Table 12:
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
Module 2 of 4
18
Notes:
1.
Power-on Reset
Program Latency
CCLK (output) Delay
Program Pulse Width
T
reaches the recommended operating voltage.
POR
12.
Description
delay is the initialization time required after V
Power-up Timing Characteristics
1
PROGRAM
T
Symbol
PROGRAM
Vcc
T
T
INIT
T
ICCK
POR
PL
Figure 20: Power-Up Timing Configuration Signals
Value
100.0
300
2.0
0.5
4.0
ms, max
µ
µ
µ
ns, min
CCINT
Units
s, max
s, max
s, min
CCLK OUTPUT or INPUT
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TPOR
M0, M1, M2
(Required)
TPL
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
TICCK
VALI
ds022_020_071201
DS025-2 (v2.1) July 17, 2002
R