XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 64

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XCV405E-7BG556I

Manufacturer Part Number
XCV405E-7BG556I
Description
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Clock Distribution Switching Characteristics
I/O Standard Global Clock Input Adjustments
Module 3 of 4
10
Notes:
1.
GCLK IOB and Buffer
Global Clock PAD to output.
Global Clock Buffer I input to O output
Data Input Delay Adjustments
Standard-specific global clock
input delay adjustments
Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see
Description
Description
(1)
T
T
T
T
GPLVCMOS18
GPLVCMOS2
T
T
T
T
T
T
Symbol
GPPCI33_3
GPPCI66_3
T
T
T
T
GLVPECL
GPSSTL2
GPSSTL3
GPLVTTL
GPGTLP
GPHSTL
GPGTL
GPCTT
GPAGP
GLVDS
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
www.xilinx.com
1-800-255-7778
Symbol
LVCMOS2
LVCMOS2
Standard
T
LVPECL
T
SSTL2
SSTL3
LVTTL
GPIO
LVDS
GTL+
HSTL
GIO
AGP
GTL
CTT
0.38
0.11
Min
Table
–0.02
–0.05
–0.05
0.12
0.23
0.23
0.20
0.20
0.18
0.21
0.18
0.22
0.21
Min
0.0
3.
0.19
0.7
Speed Grade
-8
–0.11
0.20
0.38
0.38
0.08
0.37
0.37
0.27
0.27
0.27
0.33
0.27
Speed Grade
0.0
0.0
-8
0.45
0.7
-7
–0.11
0.20
0.38
0.38
0.08
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.0
0.0
-7
DS025-3 (v2.2) July 17, 2002
0.50
0.7
-6
–0.11
0.20
0.38
0.38
0.08
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.0
0.0
-6
ns, max
ns, max
Units
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
Units
R

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