XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 17

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Table 9
each device.
Table 9:
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
For more information on serial PROMs, see the PROM data
sheet at
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
Table 10:
DS025-2 (v2.1) July 17, 2002
CCLK
XCV405E
XCV812E
Device
lists the total number of bits required to configure
http://www.xilinx.com/partinfo/ds026.pdf
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum Frequency
Frequency Tolerance, master mode with respect to nominal
R
Virtex-E Bitstream Lengths
Master/Slave Serial Mode Programming Switching
PROGRAM
# of Configuration Bits
Description
M2
PROGRAM
DONE
Figure 13: Master/Slave Serial Mode Circuit Diagram
M0 M1
3,430,400
6,519,648
VIRTEX-E
MASTER
SERIAL
DOUT
CCLK
DIN
INIT
.
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
3.3V
www.xilinx.com
4.7 K
1-800-255-7778
(Low Reset Option Used)
CLK
DATA
CE
RESET/OE
XC1701L
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected.
timing.
Table 10
shown in
INIT pins of all daisy-chained FPGAs are High.
CEO
References
N/C
Figure
Figure
provides more detail about the characteristics
shows a full master/slave system. A Virtex-E
1/2
1/2
3
4
5
Figure 14
CCLK
PROGRAM
DIN
DONE
M2
M0 M1
14. Configuration must be delayed until the
N/C
XC4000XL,
VIRTEX-E,
SLAVE
T
T
DSCK
DOUT
Symbol
DCC
INIT
T
T
T
shows slave-serial configuration
F
CCO
CCH
XCVE_ds_013
CCL
CC
/T
/T
CCD
CKDS
+45% –30%
Values
5.0/0.0
5.0/0.0
12.0
5.0
5.0
66
Module 2 of 4
MHz, max
ns, max
ns, min
ns, min
ns, min
ns, min
Units
13