LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 74

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

Figure 20 illustrates a favorable layout for ground planes
20a shows a layout using a 28-pin PLCC socket and
8 0 Analog Considerations
The LM12434 8 is designed to operate from a single
power supply The LM12 L 438 is designed to operate from
a single
pins for the analog and digital portions of the circuit allow
separate external bypassing To minimize power supply
noise and ripple adequate bypass capacitors should be
placed directly between power supply pins and their associ-
ated grounds Both supply pins are generally connected to
the same supply source In systems with separate analog
and digital supplies the DAS should be powered from the
analog supply At least a 10 F tantalum electrolytic capaci-
tor in parallel with a 0 1 F monolithic ceramic capacitor is
recommended for bypassing each power supply The key
consideration for these capacitors is to have the low series
resistance and inductance The capacitors should be placed
as close as physically possible to the supply and ground
pins with the smaller capacitor closer to the device The
capacitors also should have the shortest possible leads in
order to minimize series lead inductance Surface mount
chip capacitors are optimal in this respect and should be
used when possible
When the power supply regulator is not local on the board
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point The value of the
capacitor depends on the total supply current of the circuits
on the PC board All supply currents should be supplied by
the capacitor instead of being drawn from the external sup-
ply lines while the external supply charges the capacitor at
a steady rate
The DAS has two V
package It is recommended to use a 0 1 F plus a 10 F
capacitor between pins 15 and 16 (V
and a 0 1
(DGND) for the PLCC package The respective pins for the
SO package are 21 and 22 (V
and 7 (DGND) The layout diagrams in Section 8 8 show the
recommended placement for the supply bypass capacitors
8 8 PC BOARD LAYOUT AND GROUNDING
CONSIDERATIONS
To get the best possible performance from the LM12434
and LM12 L 438 the printed circuit boards should have
separate analog and digital ground planes The reason for
using two ground planes is to prevent digital and analog
ground currents from sharing the same path until they reach
a very low impedance power supply point This will prevent
noisy digital switching currents from being injected into the
analog ground
power supply and reference input bypass capacitors Figure
through-hole assembly Figure 20b shows a surface mount
layout for the same 28-pin PLCC package A similar ap-
proach should be used for the SO package
The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit input amplifiers signal conditioning cir-
cuits and analog signal traces
The digital ground plane should encompass the area under
the digital circuits and the digital input output pins of the
DAS Having a continuous digital ground plane under the
a
3 3V supply The separate supply and ground
F capacitor between pins 28 (V
D
a
and DGND pins on two sides of its
D
a
) and 20 (DGND) 6 (V
D
a
) and 14 (DGND)
(Continued)
D
a
) and 1
a
D
a
5V
)
74
Figure 20 also shows the reference input bypass capacitors
Figure 21 is intended to give a general idea of how the DAS
data and clock traces is very important This reduces the
overshoot undershoot and high frequency ringing on these
lines that can be capacitively coupled to analog circuitry
sections through stray capacitances
The AGND and DGND in the LM12434 and LM12 L 438
are not internally connected together They should be con-
nected together on the PC board right at the chip This will
provide the shortest return path for the signals being ex-
changed between the internal analog and digital sections of
the DAS
It is also a good design practice to have power plane layers
in the PC board This will improve the supply bypassing (an
effective distributed capacitance between power and
ground plane layers) and voltage drops on the supply lines
However power planes are not essential as ground planes
are for the performance of the DAS If power planes are
used they should be separated into two planes and the
area and connections should follow the same guidelines as
mentioned for the ground planes Each power plane should
be laid out over its associated ground planes avoiding any
overlap between power and ground planes of different
types When the power planes are not used it is recom-
mended to use separate supply traces for the V
V
output or the power entry point to the PC board) This will
help ensure that the noisy digital supply does not corrupt
the analog supply
When measuring AC input signals with the DAS any cross-
talk between analog input output lines and the reference
lines (IN0– IN7 MUXOUT
minimized Cross talk is minimized by reducing any stray
capacitance between the lines This can be done by in-
creasing the clearance between traces keeping the traces
as short as possible shielding traces from each other by
placing them on different sides of the AGND plane or run-
ning AGND traces between them
Here the reference inputs are considered to be differential
The performance of the DAS improves by having a 0 1 F
capacitor between the V
ing in a manner similar to that described in Section 8 7 for
the supply pins When a single ended reference is used
V
used between V
recommended to directly connect the AGND side of these
capacitors to the V
the ground sides of the capacitors separately to the ground
planes This provides a significantly lower-impedance con-
nection when using surface mount technology
should be wired and interfaced to a C that operates in the
Standard Interface mode All necessary analog and digital
power supply and voltage reference bypass capacitors are
shown A voltage reference of 4 096V generated by the
LM4040-4 1 is connected to the V
V
pins P1 through P5 of the DAS are connected to the
serial control lines and the interrupt pin of the DAS is wired
directly to the interrupt of the
runs on a separate clock than the
applications the DAS analog clock (CLK) may be a deriva-
tive of the C’s clock
D
REF
REF
a
b
b
pins from a low impedance supply point (the regulator
is connected to analog ground The serial interface
is connected to AGND and only two capacitors are
REF
REF
a
b
and V
REF
instead of connecting V
g
a
S H IN
REF
and V
C In this diagram the DAS
b
REF
(0 1 F
g
REF
a
C however in some
of the DAS and the
V
b
REF g
and by bypass-
a
10 F) It is
) should be
REF
A
a
b
and
and
C’s