LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 27

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

6 0 Operational Information
Acquisition Time
The LM12434 and LM12 L 438’s internal S H is designed
to operate at its minimum acquisition time (1 125 1 5
for a 12-bit
ance R
MHz) When 60 80
nal S H’s acquisition time can be increased to a maximum
of 4 88 6 5
provide sufficient time for the sampling capacitor to charge
See Section 6 2 1 (Instruction RAM ‘‘00’’) Bits 12 – 15 for
more information
Instruction Register
The INSTRUCTION RAM is divided into 8 separate words
each with 48 (3 x 16) bit length Each word is separated into
three 16-bit sections Each word has a unique address and
different sections of the instruction word are selected by the
2-bit RAM pointer (RP) in the configuration register As
shown in Figure 7 the Instruction RAM sections are labeled
Instructions Limits
tion holds operational (12-bit
dog) information such as the input channels to be selected
the mode of operation to be performed for each instruction
and the duration of the acquisition period The other two
sections are used in the watchdog mode and the user-
defined limits are stored in them Each watchdog instruction
has 2 limits associated with it (usually a low limit and a high
limit but two low limits or two high limits may be pro-
grammed instead) The DAS starts executing from instruc-
tion 0 and moves through the next instructions up to any
user-specified instruction and then ‘‘loop back’’ to instruc-
tion 0 It is not necessary to execute all 8 instructions in the
instruction loop The cycle may be repeatedly executed until
stopped by the user The processor should access the In-
struction RAM only when the instruction sequencer is
stopped
FIFO Register
The FIFO Register stores the conversion results This regis-
ter is ‘‘Read only’’ and all the locations are accessed
through a single address Each time a conversion is per-
formed the result is stored in the FIFO and the FIFO’s inter-
nal write pointer points to the next location The pointer rolls
back to location 1 after a Write to location 32 The same
flow occurs when reading from the FIFO The internal FIFO
Writes and the external FIFO Reads do not affect each oth-
er’s pointer locations
S
is less than or equal to 60 80
a
sign conversion) when the source imped-
s (12
1 and Limits
a
k
sign bits f
R
S s
a
sign 8-bit
4 17 5 56 k
CLK
2 The Instruction sec-
e
a
8 6 MHz) to
(f
sign or watch-
(Continued)
CLK s
the inter-
8 6
s
27
Microprocessor overhead is reduced through the use of the
internal conversion FIFO Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention The microprocessor can at
any time interrogate the FIFO and retrieve its contents It
can also wait for the LM12434 and LM12 L 438 to issue an
interrupt when the FIFO is full or after any number (
conversions have been stored
Configuration Register
The CONFIGURATION Register is the main ‘‘control panel’’
of the DAS Writing 1s and 0s to the different bits of the
Configuration Register commands the DAS start or stop the
sequencer reset the pointers and flags go into ‘‘standby’’
mode for low power consumption calibrate offset and lin-
earity and select sections of the RAM
Other Registers
The INTERRUPT ENABLE Register lets the user activate up
to 7 sources for interrupt generation (refer to Section 6 2 3)
It also holds two user-programmable values One is the
number of conversions to be stored in the FIFO register
before the generation of the Data Ready interrupt The other
value is the instruction number that generates an interrupt
when the sequencer reaches that instruction
The INTERRUPT STATUS and LIMIT STATUS Registers
are ‘‘Read only’’ registers They are used as vectors to indi-
cate which conditions have generated the interrupt and
what watchdog limit boundaries have been passed Note
that the bits are set in the status registers upon occurrence
of their corresponding interrupt conditions regardless of
whether the condition is enabled for external interrupt gen-
eration
The TIMER Register can be programmed to insert a delay
before execution of each instruction A bit in the instruction
register enables or disables the insertion of the delay before
the execution of an instruction
Serial I O
A very flexible serial synchronous interface is provided to
facilitate reading from and writing to the LM12434 and
LM12 L 438’s registers The communication between the
LM12434 and LM12 L 438 and microcontrollers micro-
processors and other circuitry is accomplished through this
serial interface The serial interface is designed to directly
communicate with the synchronous serial interfaces of the
most popular microprocessors with no extra hardware re-
quirement The interface has been also designed to simplify
software development
s
32) of