LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 37

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

6 0 Operational Information
they are not masked (by the Interrupt Enable register) The
Interrupt Status register is then read to determine which of
the seven interrupts has been issued
The Interrupt Status register must be cleared by reading it
after writing to the Interrupt Enable register This removes
any spurious interrupts on the INT pin generated during an
Interrupt Enable register access
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12434 and LM12 L 438 are operating in the ‘‘watch-
dog’’ comparison mode Two sequential comparisons are
made when the LM12434 and LM12 L 438 are executing a
‘‘watchdog’’ instruction Depending on the logic state of Bit
9 in the Instruction RAM’s second and third sections an
interrupt will be generated either when the input signal’s
magnitude is greater than or less than the programmable
limits (See the Instruction RAM Bit 9 description ) The Limit
Status register will indicate which preprogrammed limit ( 1
or
when the limit was crossed
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10 This flag appears before the instruc-
tion’s execution Instructions continue to execute as pro-
grammed
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11– 15 This
value ranges from 00000 to 11111 with 00001 to 11111
representing 1 to 31 conversions stored in the FIFO and
00000 generating an interrupt after 32 conversions See
Section 6 2 8 for more FIFO information
The completion of the short single-sampled auto-zero cali-
bration generates Interrupt 3
The completion of a full auto-zero and linearity self-calibra-
tion generates Interrupt 4
Interrupt 5 is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM
‘‘00’’) set to ‘‘1’’
Interrupt 7 is issued after a short delay (10 ms typ) while
the DAS returns from Standby mode to active operation us-
ing the Configuration register’s Bit 4 This short delay allows
the internal analog circuitry to settle sufficiently ensuring
accurate conversion results (see Note 22)
6 2 4 Interrupt Enable Register
The Interrupt Enable register at address location 1001
has READ WRITE capability An individual interrupt’s ability
to produce an external interrupt at pin 31 (INT) is accom-
plished by placing a ‘‘1’’ in the appropriate bit location Any
of the internal interrupt-producing operations will set their
corresponding bits to ‘‘1’’ in the Interrupt Status register re-
gardless of the state of the associated bit in the Interrupt
Enable register See Section 2 3 for more information about
each of the eight internal interrupts
Bit 0 enables an external interrupt when an internal ‘‘watch-
dog’’ comparison limit interrupt has taken place
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt
Enable register
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit stored in Bits 11–15 of the Interrupt Enable
register has been reached
2) was crossed and which instruction was executing
(Continued)
37
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated
Bit 6 don’t care condition
Bit 7 enables an external interrupt when the LM12434 and
LM12 L 438 returns from standby to active mode (see
Note 22)
Bits 8– 10 form the storage location of the user-programma-
ble value against which the Sequencer’s address is com-
pared When the Sequencer reaches an address that is
equal to the value stored in Bits 8– 10 an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register If Bit 1 of the Interrupt Enable register is set to ‘‘1’’
an external interrupt will appear at pin 31 (INT)
The value stored in bits 8– 10 ranges from 000 to 111 rep-
resenting 1 to 8 instructions stored in the Instruction RAM
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’ the Sequencer is started by placing
a ‘‘1’’ in the Configuration register’s START bit Setting the
INT 1 trigger value to 000 does not generate an INT 1 the
first time the Sequencer retrieves and decodes Instruction
000 The Sequencer generates INT 1 (by placing a ‘‘1’’ in
the Interrupt Status register’s Bit 1) the second time and
every subsequent time that the Sequencer encounters In-
struction 000 It is important to remember that the Sequenc-
er continues to operate even if an Instruction interrupt (INT
1) is internally or externally generated The only mecha-
nisms that stop the Sequencer are an instruction with the
PAUSE bit set to ‘‘1’’ (halts before instruction execution)
placing a ‘‘0’’ in the Configuration register’s START bit or
placing a ‘‘1’’ in the Configuration register’s RESET bit
Bits 11– 15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt This internal interrupt appears in Bit 2 of the
Interrupt Status register If Bit 2 of the Interrupt Enable reg-
ister is set to ‘‘1’’ an external interrupt will appear at pin 31
(INT)
6 2 5 Interrupt Status Register
This read-only register is located at address 1010 The cor-
responding flag in the Interrupt Status register goes high
(‘‘1’’) any time that an interrupt condition takes place
whether an interrupt is enabled or disabled in the Interrupt
Enable register Any of the active (‘‘1’’) Interrupt Status reg-
ister flags are reset to ‘‘0’’ whenever this register is read or
a device reset is issued (see Bit 1 in the Configuration Reg-
ister)
Bit 0 is set to ‘‘1’’ when a ‘‘watchdog’’ comparison limit
interrupt has taken place
Bit 1 is set to ‘‘1’’ when the Sequencer has reached the
address stored in Bits 8– 10 of the Interrupt Enable register
Bit 2 is set to ‘‘1’’ when the Conversion FIFO’s limit stored
in Bits 11– 15 of the Interrupt Enable register has been
reached
Bit 3 is set to ‘‘1’’ when the single-sampled auto-zero has
been completed
Bit 4 is set to ‘‘1’’ when an auto-zero and full linearity self-
calibration has been completed
Bit 5 is set to ‘‘1’’ when a Pause interrupt has been generat-
ed