LM12434CIWM NSC [National Semiconductor], LM12434CIWM Datasheet - Page 62

• Manufacturer Part Number: LM12434CIWM
• Description: Sign Data Acquisition System with Serial I/O and Self-Calibration
• Manufacturer: NSC [National Semiconductor]

7 0 Digital Interface
7 3 TMS320 INTERFACE MODE
The TMS320 interface mode is designed to work directly
with the serial interface port of the TMS320C3x and
TMS320C5x families of digital signal processors This inter-
face uses five lines two data lines (DX DR) two frame
synchronization signal lines (FSX FSR) and a serial clock
line (SCLK) Note that the TMS320C3x 5x serial interface
has two separate serial clock lines for transmit and receive
called CLKX and CLKR but the LM12434 and LM12 L 438
only uses one clock input for both receive and transmit
Typically CLKX is specified as an output and drives SCLK
as well as CLKR (defined as an input) The serial clock for
this interface mode is a free running clock with the data
stream synchronized by SCLK The start of each data trans-
fer (the beginning of a data packet) is synchronized by FSX
(Transmit Frame Sync) or FSR (Receive Frame Sync) This
interface can communicate with one device no device se-
lect signal is used The following discussion assumes that
the reader has a basic knowledge of the architecture and
operation of the TMS320C3x 5x serial interface port
The TMS320 interface mode is selected when the
MODESEL1 and MODESEL2 pins have the logic state of
‘‘11’’ Figure 16 shows a typical connection diagram for the
LM12434 and LM12 L 438 in the TMS320 serial interface
mode The FSR FSX DX DR and SCLK lines are assigned
to interface pins P1 through P5
Data transfer in this mode is programmable by the proces-
sor for 8-
TMS320C3x and 8- or 16-bit data packets for TMS320C5x
The LM12434 and LM12 L 438 uses 16-bit and 32-bit data
packets For the TMS320C5x the 32-bit packet is composed
of two successive 16-bit packets with no gaps between
them The data bits in each packet are transferred MSB
first and are shifted in on the rising edge of SCLK and are
stable and captured at the falling edge of the SCLK As with
the ‘‘Standard’’ and ‘‘8051’’ interface modes the LM12434
and LM12 L 438 has three different communication cycles
write cycle read cycle and burst read cycle At the start of
each data transfer cycle a stream of 9 data bits (the ‘‘com-
mand packet’’) is written to the LM12434 and LM12 L 438
and informs it about the communication cycle The place-
ment of these 9 bits in the data packet is different in the
read and write cycles and is discussed for each case sepa-
rately The command packet carries the following informa-
tion
what type of data transfer (communication cycle) is start-
ed
which device register is to be accessed
16-
24-
or 32-bit data packets for the
(Continued)
62
Figure 15 shows the timing diagrams for the three communi-
The command packet has the following format
The first bit of the command packet is always the MSB of
the data packet to to be transferred
cation cycles Figure 15a shows a write cycle Figure 15b
shows a read cycle and Figure 15c shows a burst read
cycle Note that these timing diagrams depict general rela-
tionships between the SCLK edges the data bits and the
frame synchronization signals (FSX FSR) These diagrams
are not meant to show guaranteed timing performance
(See specification tables for parametric switching character-
istics )
Write cycle A write cycle begins with an FSX pulse from
the processor The first data bit is received by the DAS on
the DX line during the next SCLK falling edge after the fall-
ing edge of FSX A 32-bit data packet is written to the DAS
The TMS320C3x does this with a 32-bit transfer using its
serial port 32-bit register With the TMS320C5x family two
successive 16-bit transfers are initiated without any gap in
between The first 9 bits (MSBs) of the data are the com-
mand packet with the R W bit and B bit equal to zero Fol-
lowing the command packet a 16-bit data stream starts on
the falling edge of the 10th SCLK cycle and continues
through the 25th cycle The last 7 bits in the 32-bit data
packet are ‘‘don’t care’’ and are ignored by the DAS The
data is written to the register addressed in the command
packet (A3 A2 A1 A0) There is no activity on the FSR and
DR lines during a write cycle The write cycle is completed
after the last data bit is transferred
Read cycle A read cycle also begins with an FSX pulse
from the processor The read cycle uses 16-bit data trans-
fer Following the FSX pulse 16 bits of data are written to
the DAS on the DX line The first 9 bits (MSBs) of data are
the command packet with the R W bit equal to one and the
B bit equal to zero The last 7 bits (LSBs) are ‘‘don’t care’’
and are ignored by the DAS About 3 to 4 CLK (the DAS
main clock input not the SCLK) cycles after the R W bit is
received the DAS generates an FSR pulse to initiate the
data transfer Following the FSR pulse the DAS will send
16 bits of data to the processor on the DR line The first bit
(MSB) of the data appears on the DR line on the next SCLK
cycle following the FSR pulse The data is read from the
register addressed in the command packet The read cycle
is completed after the last data bit is transferred
TL H 11879 – 54