AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 29

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Digitally controlling the slew rate of the output is necessary to
meet the analog rate of change requirements for HART.
SLEW RATE CONTROL
The Slew Rate Control feature of the AD5755-1 allows the user
to control the rate at which the output value changes. This
feature is available on both the current and voltage outputs.
With the slew rate control feature disabled the output value will
change at a rate limited by the output drive circuitry and the
attached load. If the user wishes to reduce the slew rate this can
be achieved by enabling the slew rate control feature. With the
feature enabled via the SREN bit of the Slew Rate Control
Register, (See Table 27) the output, instead of slewing directly
between two values, will step digitally at a rate defined by two
parameters accessible via the Slew Rate Control Register as
shown in Table 27. The parameters are SR_CLOCK and
SR_STEP. SR_CLOCK defines the rate at which the digital slew
will be updated, e.g. if the selected update rate is 8KHz the
output will update every 125µs, in conjunction with this the
SR_STEP defines by how much the output value will change at
each update. Together both parameters define the rate of change
of the output value. Table 33 and Table 34 outline the range of
values for both the SR_CLOCK and SR_STEP parameters.
Table 33. Slew Rate Update Clock Options
*Clock Frequencies accurate to ±TDB%.
SR_CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)*
0.5Hz
64K
32K
16K
500
250
125
8k
4k
2k
1k
64
32
16
8
4
Rev. PrD | Page 29 of 34
Table 34. Slew_Rate Step Size Options
The following equation describes the slew rate as a function of
the step size, the update clock frequency and the LSB size.
Where:
Slew T ime is expressed in seconds
Output Change is expressed in Amps for I
W hen the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, for example
if the CLEAR pin is asserted the output will slew to the clear
value at the programmed slew rate (assuming that Clear
channel is enabled to be cleared). T he update clock
frequency for any given value will be the same for all output
ranges, the step size however will vary across output ranges for
a given value of step size as the LSB size will be different for
each output range.
POWER DISSIPATION CONTROL
The AD5755-1 contains integrated dynamic power control
using a DC-DC boost circuiot allowing reductions in power
consumption from standard designs when using the part in
current output mode.
In standard current input module designs the load resistor
values can range from typically 50 ohm to 750 ohm. Output
module systems must source enough voltage to meet the
compliance voltage requirement across the full range of load
resistor values. For example, in a 4-20ma loop when driving
20ma a compliance voltage of >15V is required. When driving
20ma into a 50 ohm load only 1V compliance is required.
The AD5755-1 circuitry senses the output voltage and regulates
this voltage to meet compliance requirements plus a small
headroom voltage.
DC-DC CONVERTERS
The AD5755-1 contains 4 independent DCDC converters.
These are used to provide dynamic control of the V
voltage for each channel (See Figure 15). Figure 21 below shows
the discreet components needed for the DCDC circuitry and
Slew
Time
SR_STEP
000
001
010
011
100
101
110
111
=
Step
Size
×
Update
AD5755-1 (16 BIT)
Step Size (LSBs)
Output
Clock
128
256
16
32
64
1
2
4
Change
Frequency
OUT
or V olts for V
AD5755-1
×
LSB
boost
Size
supply
OUT