AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 22

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

AD5755-1
CONTROL REGISTERS
When writing to a data register the following format must be used:
Table 17. Writing to a control register
MSB
D23
R/ W
See
1, DREG0=1 and then setting the CREG2, CREG1 and CREG0 bits to the appropriate decode address for that register as per Table 18
below. These CREG bits select between the various control registers.
Table 18. Register Access Decode
CREG2, (D15)
0
0
0
0
1
MAIN CONTROL REGISTER
CREG2, CREG1, CREG0 are set to ‘0,0,1’ to select the Main Control Register. The Main Control Register options are shown below.
Table 19. Programming the Main Control Register
Table 20. Main Control Register Functions.
Option
STATREAD
POC
OUTEN ALL
DC_DCALL
ShtCctLim
EWD
WD1, WD0
MSB
D15
0
Table 10
D22
DUT_AD1 DUT_AD0 1
D14
0
for configuration on bits D23 to D16. The control registers are addressed by setting the DREG bits to DREG2 = 1, DREG1 =
D13
1
CREG1, (D14)
0
0
1
1
0
D21
D12
POC
D20 D19 D18 D17
STATREAD
Description
Enable status readback during a write. See Features section.
STATREAD =0, Disable
The POC bit decides the state of the VOUT channel during normal operation. It’s default value is 0.
POC Bit = 0. The output will go to the value set by the POC pin when the current out channel is enabled.
POC Bit = 1. The output will go to the opposite value of the POC pin if the channels I
Enables the output on all 4 DAC simultaneously.
Do not use the OUTEN ALL bit when using the OUTEN bit in the DAC Control Registers.
When set, Powers up the DC-DC on all 4 channels Simultaneously.
To Power down the DC-DCs all channels outputs must first be disabled.
Do not use the DC_DCALL bit when using the DC_DC bit in the DAC Control Registers.
Programmable Short Circuit Limit on V
0=15ma
1=8ma
Enable Watchdog Timer. See features section for more information.
EWD=1, Enable Watchdog
EWD=0, Disable Watchdog
Timeout Select Bits. Used to select timeout period for watchdog timer.
D11
STATREAD =1, Enable
WD1
0
0
1
1
1
CREG0, (D13)
0
1
0
1
0
1
WD0
0
1
0
1
D10
EWD
DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0
5ms
10ms
100ms
200ms
WD1
Slew Rate Control Register (one per channel)
Main Control Register
DAC Control Register (one per channel)
DC-DC Control Register
Software Register (one per channel)
D9
Rev. PrD | Page 22 of 34
WD0
D16
D8
D7
X
out
D15
pin in the event of a short circuit condition.
ShtCctLim
D6
D14
OUTEN ALL
D13
Preliminary Technical Data
D5
LSB
D12to D0
DC-DC ALL
D4
out
is enabled.
D3 to D0
LSB
X