AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 20

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

AD5755-1
DATA REGISTERS
The input register is 24 bits wide. When writing to a data register the following format must be used:
Table 9.
D23 D22
R/ W DUT_AD1
Table 10.
Register
R/ W
DUT_AD1, DUT_AD0
DREG2, DREG1,
DREG0
DAC_AD1, DAC_AD0
DAC DATA REGISTER
Table 11. Programming the AD5755-1 DAC Data Registers
When writing to the AD5755-1 DAC Data Registers D15-D0 are used for DAC DATA bits. See Table x for input register decode.
MSB
D23
R/ W
GAIN REGISTER
The Gain Register stores the Gain Code (M) which is used in the DAC transfer function to calculated the overall DAC input code (see
formula below). The Gain Register is addressed by setting DREG bits to ‘0,1,0’ . The DAC address bits select which DAC channel the gain
write is addressed to. It is possible to write the same gain code to all 4 DAC channels at the same time by setting the DREG bits to 011.
The AD5755-1 Gain Register is a 16/12 bit register (bits G15.. G0/G3) and allows the user to adjust the gain of each channel in steps of 1
LSB as shown in the Table below. The Gain Register coding is straight binary. In theory the gain can be tuned across the full range of the
output. In practice, the maximum recommended gain trim is about 50% of programmed range in order to maintain accuracy.
D22
DUT_AD1
AD5755-1 Writing to a Data Register
AD5755-1 Input Register Decode
D21
DUT_AD0
D21
DUT_AD0
Function
Indicates a read from or a write to the addressed register.
Used in association with External Pins AD1, AD0 to determine which AD5755-1 device is being addressed by the
system controller.
DUT_AD1
0
0
1
1
Selects whether a data register or a control register is written to. If a control register is selected, a further decode
of CREG bits is required to select the particular control register, as detailed below.
DREG2
0
0
0
1
1
1
1
These bits are used to decode the DAC channel
DAC_AD1
0
0
1
1
X
D20
DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0
D20
DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA
DREG1
0
1
1
0
0
1
1
DUT_AD0
0
1
0
1
DAC_AD0
0
1
0
1
X
D19
D19
D18
D18
DREG0
0
0
1
0
1
0
1
DAC Channel/ Register Address
DAC A
DAC B
DAC C
DAC D
These are don’t cares if they are not relevant to the operation being performed.
Rev. PrD | Page 20 of 34
D17
D17
Function
Addresses Part with Pins AD1=0, AD0=0
Addresses Part with Pins AD1=0, AD0=1
Addresses Part with Pins AD1=1, AD0=0
Addresses Part with Pins AD1=1, AD0=1
Function
Write to DAC Data Register (Individual Channel Write)
Write to Gain Register
Write to Gain Register (ALL DACS)
Write to Offset Register
Write to Offset Register (ALL DACS)
Write to Clear Code Register
Write to a Control Register
D16
D16
D15 to D0
LSB
D15 to D0
Preliminary Technical Data