AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 28

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

AD5755-1
ASYNCHRONOUS CLEAR
CLEAR is an active high edge sensitive input that allows the
output to be cleared to a pre programmed 16 bit code. This code
is user programmable via a per-channel 16 bit Clear Code
Register.
In order for a channel to clear, that channel must be enabled to
be cleared via the CLR_EN bit in the channels DAC Control
Register. If the channel is not enabled to be cleared then the
output will remain in its current state independent of the
CLEAR pin level.
When the CLEAR signal is returned low, the relevant outputs
remains cleared until a new value is programmed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5755-1 offers the option of packet error
checking based on an 8-bit (CRC-8) cyclic redundancy check.
The device controlling the AD5755-1 should generate an 8-
frame check sequence using the polynomial
This is added to the end of the data word, and 32 bits are sent to
the AD5755-1 before taking SYNC high. If the AD5755-1 sees a
32-bit frame, it will perform the error check when SYNC goes
high. If the check is valid, then the data will be written to the
selected register. If the error check fails, the FAULT pin will go
low and the PEC ERROR bit in the Status Register will be set.
After reading the Status Register, FAULT will return high
(assuming there are no other faults) and the PEC ERROR bit
will be cleared automatically.
The PEC can be used for both transmit and receive of data
packets. If Status Readback During Write is enabled, the ‘PEC’
values returned during the Status Readback During Write
should be ignored. All other PEC values will be valid though
and the user can still use the normal readback operation to
monitor Status Register activity.with PEC.
WATCHDOG TIMER
If enabled, an on chip watchdog timer will generate an alert
signal if 0x195 has not been written to the Software Register
within the programmed timeout period. This feature is useful to
ensure communication has not been lost between the MCU and
the AD5755-1 and that these datapath lines are working
properly (i.e. SDI/SCLK/SYNC). If 0x195 is not received by the
Software Register within the timeout period, the ALERT pin
will signal a fault condition. The ALERT signal is active high
and can be connected directly to the CLEAR pin to enable a
CLEAR in the event that data communications are lost from the
MCU.
C
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Rev. PrD | Page 28 of 34
The watchdog timer is enabled and the timeout period
(50,100,150 or 200ms) set in the control register (See Table 19).
OUTPUT ALERT
The AD5755-1 is equipped with a ALERT pin, this is An active
high CMOS output. The AD5755-1 has an internal watchdog
timer. If enabled, it will monitor SPI communications. If 0x195
is not received by the Software Register within the timeout
period, the ALERT pin will go active.
INTERNAL REFERENCE
The AD5755-1 contains an integrated +5V voltage reference
with initial accuracy of ±2mV max and a temperature drift
coefficient of ±5 ppm max. The reference voltage is buffered
and externally available for use elsewhere within the system.
EXTERNAL CURRENT SETTING RESISTOR
Referring toFigure 15, R1 is an internal sense resistor as part of
the voltage to current conversion circuitry. The stability of the
output current value over temperature is dependent on the
stability of the value of R1. As a method of improving the
stability of the output current over temperature an external
15kΩ low drift resistor can be connected to the R
AD5755-1 to be used instead of the internal resistor R1. The
external resistor is selected via the DAC Control register. See
Table 21.
HART
The AD5755-1 has 4 CHART pins, one corresponding to each
output channels. A HART signal can be coupled into these pins.
The HART signal will appear on the corresponding current
output, if the output is enables. Table 32 below shows the
recommended input voltages for the HART signal at the
CHART pin. If these voltages are used the current output
should meet the HART amplitude specifications. Figure 20 is
the recommended circuit for attenuating and coupling in the
HART signal.
Table 32. CHART input voltage to HART output current
Internal Rset
External Rset
A minimum capacitance of C1+C2 will be required to ensure
that the 1.2kHz and 2.2kHz “HART frequencies” are not
significantly attenuated at the output. This will be in the order
of 10’s of nF’s.
HART modem
output
CHART input voltage
150mVp-p
170mVp-p
C1
Figure 20. Coupling HART signal
Preliminary Technical Data
C2
CHART
Current output (HART)
1mAp-p
1mAp-p
SET
pin of the