AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 12

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

AD5755-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
R
R
REFGND
REFGND
ADO
AD1
SYNC
SCLK
SDIN
SDO
DV
DGND
LDAC
CLEAR
SET_B
SET_A
DD
RSETB
RSETA
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
ALERT
FAULT
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Description
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
I
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
I
Ground Reference Point for Internal Reference.
Ground Reference Point for Internal Reference.
Address decode for the DUT on the board.
Address decode for the DUT on the board.
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock
speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 3 and Figure 4.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Digital Ground Pin.
Load DAC. Active Low Input. This is used to update the DAC registers and consequently the analog
outputs. When tied permanently low the addressed DAC register is updated on the rising edge of SYNC . If
LDAC is held high during the write cycle the DAC input register is updated but the output update only
takes place at the falling edge of LDAC . See Figure 2. Using this mode all analog outputs can be updated
simultaneously. The LDAC pin must not be left unconnected.
Active High, Edge Sensitive Input. Asserting this pin sets the Output Current/Voltage to the pre-
programmed CLEAR CODE. Only channels enabled to be cleared will be cleared. See features section for
OUT_B
OUT_A
PIN 1
INDICATOR
temperature drift performance. See the Features section.
temperature drift performance. See the Features section.
64 LFCSP
Figure 6. 64 LFCSP Pin Configuration
Rev. PrD | Page 12 of 34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMPDCDC_C
IOUTC
VBOOSTC
AVCC
GND_SWC
GND_SWD
AVSS
VBOOSTB
SWC
SWD
SWA
GND_SWA
GND_SWB
SWB
AGND
IOUTB
Preliminary Technical Data