AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 21

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AD5755-1x

Manufacturer Part Number
AD5755-1x
Description
Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
Manufacturer
AD [Analog Devices]
Datasheet
Preliminary Technical Data
Table 12. Programming the AD5755-1 Gain Register
R/ W
Table 13. AD5755-1 Gain Register
Gain Adjustment
+65535 LSBs
+65534 LSBs
1 LSBs
0 LSBs
OFFSET REGISTER
The Offset Register is addressed by setting the DREG BITS to DREG2 =1 DREG1=0, DREG0=0. The DAC address bits select with which
DAC channel the offset write is addressed to. It is possible to write the same offset code to all 4 DAC channels at the same time by setting
the DREG bits to 101. The AD5755-1 offset code is 16/12 bit (bits OF15.. OF0/OF3) and allows the user to adjust the offset of each
channel by −32768/8192 LSBs to +32767/8191 LSBs in steps of 1 LSB as shown in the Table below.. The Offset Register coding is straight
binary. The default code in the Offset Register is 0x8000/0x800. This will result in zero offset programmed to the output.
Table 14. Programming the AD5755-1 Offset Register
R/ W
0
Table 15. AD5755-1 Offset Register options
Offset Adjustment
+32768 LSBs
+32767 LSBs
No Adjustment (default)
−32767 LSBs
−32768 LSBs
CLEAR CODE REGISTER
There is a per channel Clear Code Register. The Clear Code Register is 16 bits wide and is addressed by setting the DREG bits to’1,1,0’ . It
is also possible, via software, to enable/disable on a per channel basis which channels will be cleared when the CLEAR pin is activated.
The default clear code is all 0’s. See Features section for more information.
Table 16. Programming AD5755-1 Clear Code Register
D23
R/ W
0
0
DUT_
AD1
DEVICE ADDRESS
D22
DUT_AD1
DEVICE ADDRESS
DUT_
AD1
DEVICE ADDRESS
DUT_
AD0
DUT_
AD0
D21
DUT_AD0
DREG2
100
DREG2
D20
DREG2
110
G15
1
1
-
0
0
DREG1
OF15
1
1
-
1
-
0
0
DREG1
010
D19
DREG1
DREG0
G14
1
1
-
0
0
OF14
1
1
-
0
-
0
0
DREG0
D18
DREG0
DAC_
AD1
DAC Channel Address
G13
1
1
-
0
0
OF13
1
1
-
0
-
0
0
Rev. PrD | Page 21 of 34
DAC_
AD1
DAC Channel Address
D17
DAC_AD1
DAC Channel Address
0
0
G12 to G4
1
1
-
OF12 to OF4
1
1
-
0
-
0
0
DAC_
AD0
D16
DAC_AD0
DAC_
AD0
D15 to D0
OF15 to OF0
D15 to D0
CLEAR CODE
DATA
D15-D0
G15 to G0
G3
1
1
-
0
0
OF3
1
1
-
0
-
0
0
G2
1
1
-
0
0
OF2
1
1
-
0
-
0
0
G1
1
0
-
0
0
OF1
1
0
-
0
-
0
0
G0
1
0
-
1
0
OF0
1
0
-
0
-
0
0
AD5755-1

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