AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 25

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
READBACK OPERATION
Readback mode is invoked by setting the R/ W bit = 1 in the serial input register write. With R/ W = 1, bits DUT_AD1, DUT_AD0, in
association with bits RD4, RD3, RD2, RD1, RD0 (See Table 29), select the register to be read. The remaining data bits in the write
sequence are don’t care. During the next SPI transfer, the data appearing on the SDO output contains the data from the previously
addressed register. The readback diagram in Figure 3 shows the readback sequence.
Table 28. Input Shift Register Contents for a read operation
D23
R/ W DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0
Table 29. Read Address Decoding
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Read Back Example
To read back the Gain Register of Device #1 Channel A on the AD5755-1, the following sequence should be implemented:
1. Write 0xA80000 to the AD5755-1 input register. This configures the AD5755-1 device address #1 for read mode with the Gain Register
2.
of channel A selected.. Note that all the data bits, D15 to D0, are don’t care.
Follow this with any read/write command. During this command, the data from the selected Gain Register is clocked out on the SDO
line.
D22
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
D21
D20 D19 D18 D17 D16
RD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Function
Read DACA Data Register
Read DACB Data Register
Read DACC Data Register
Read DACD Data Register
Read Control Register DAC A
Read Control Register DAC B
Read Control Register DAC C
Read Control Register DAC D
Read Gain Register A
Read Gain Register B
Read Gain Register C
Read Gain Register D
Read Offset Register A
Read Offset Register B
Read Offset Register C
Read Offset Register D
Clear Code Register DAC A
Clear Code Register DAC B
Clear Code Register DAC C
Clear Code Register DAC D
Slew Rate Control Register DAC A
Slew Rate Control Register DAC B
Slew Rate Control Register DAC C
Slew Rate Control Register DAC D
Read Status Register
Read Main Control Register
Read DC-DC Control Register
Rev. PrD | Page 25 of 34
D15 to D0
X
AD5755-1