DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 50

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

Watchdog Control (WDCON)
SFR D8h
SMOD
Bit 7
POR
Bit 6
EPFI
Bit 5
PFI
Bit 4
SMOD
RW-0
7
R=Unrestricted Read, W=Unrestricted Write, T=Timed Access Write Only,
Serial Modification. This bit controls the doubling of the serial port 1 baud rate
in modes 1, 2, and 3.
0 = Serial port 1 baud rate operates at normal speed
1 = Serial port 1 baud rate is doubled.
Power-on Reset Flag. This bit indicates whether the last reset was a power-on
reset. This bit is typically interrogated following a reset to determine if the reset
was caused by a power-on reset. It must be cleared by a Timed Access write
before the next reset of any kind or the software may erroneously determine that
another power-on reset has occurred. This bit is set following a power-on reset
and unaffected by all other resets. Note: This bit is not Timed Access protected
on the DS80C310.
0 = Last reset was from a source other than a power-on reset
1 = Last reset was a power-on reset.
Enable Power fail Interrupt. This bit enables/disables the ability of the internal
band-gap reference to generate a power-fail interrupt when V
approximately 4.5 volts. While in Stop mode, both this bit and the Band-gap
Select bit, BGS (EXIF.0), must be set to enable the power-fail interrupt.
0 = Power-fail interrupt disabled.
1 = Power-fail interrupt enabled during normal operation. Power-fail interrupt
enabled in Stop mode if BGS is set.
Power fail Interrupt Flag. When set, this bit indicates that a power-fail
interrupt has occurred. This bit must be cleared in software before exiting the
interrupt service routine, or another interrupt will be generated. Setting this bit in
software will generate a power-fail interrupt, if enabled.
RW-*
POR
6
RW-0
EPF1
-n=Value after Reset, *=See Description
5
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RW-*
PFI
4
WDIF
RW-0
3
High-Speed Microcontroller User’s Guide
WTRF
RW-*
2
RW-*
EWT
1
CC
falls below
RW-0
RWT
0