DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 107

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

SECTION 9: INTERRUPTS
The High-Speed Microcontroller family utilizes a three-priority interrupt system.
interrupts varies according to the specific device. Each source has an independent priority bit, flag,
interrupt vector, and enable. In addition, interrupts can be globally enabled (or disabled). The system is
compatible with the original 8051 family. All of the original interrupts are available.
Several new sources have been added with new associated control and status bits, and new interrupt
vectors. Note that the interrupt vector table can extend from 0000h to 006Bh, so existing code may
require a relocation of the start address to avoid a conflict with the upper end of the vector table. A
summary of all interrupts appears in Table 9-1 below.
incorporates several interrupt vectors whose locations differ from those used by the High-Speed
Microcontroller Family or other 8051 derivatives.
* Cleared automatically by hardware when the service routine is vectored to.
** If edge triggered, cleared automatically by hardware when the service routine is vectored to. If level
INTERRUPT OVERVIEW
An interrupt allows the software to react to unscheduled or asynchronous events. When an interrupt
occurs, the CPU is expected to “service” the interrupt. This service takes the form of an Interrupt Service
Routine (ISR). The ISR resides at a predetermined address as shown in Table 9-1. When the interrupt
occurs, the CPU will vector to the appropriate location. It will run the code found at this location, staying
in an interrupt service state until done with the ISR. Once an ISR has begun, it can be interrupted only by
a higher priority interrupt. The ISR is terminated by a return from interrupt instruction (RETI). When an
RETI is performed, the processor will return to the instruction that would have been next when the
interrupt occurred.
INTERRUPT SUMMARY Table 9-1
Power–fail Indicator
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Interrupt
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
Real –Time Clock
Unless marked these flags must be cleared manually by software.
triggered, flag follows the state of the pin.
INTERRUPT
Serial Port 0
Serial Port 1
INTERRUPT
VECTOR
0Bh
1Bh
2Bh
3Bh
4Bh
5Bh
6Bh
33h
03h
13h
23h
43h
53h
63h
PRIORITY
NATURAL
10
11
12
13
0
1
2
3
4
5
6
7
8
9
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WDIF (WDCON.3)
RI_0 (SCON0.0),
RI_1 (SCON1.0),
RTCIF (RTCC.1)
PFI (WDCON.4)
IE0 (TCON.1)**
IE1 (TCON.3)**
TI_0 (SCON0.1)
TI_1 (SCON1.1)
TF0 (TCON.5)*
TF1 (TCON.7)*
TF2 (T2CON.7)
IE2 (EXIF.4)
IE3 (EXIF.5)
IE4 (EXIF.6)
IE5 (EXIF.7)
FLAG
Note that the D587C550 microcontroller
High-Speed Microcontroller User’s Guide
ERTCI (EIE.5)
EWDI (EIE.4)
(WDCON.5)
EX2 (EIE.0)
EX3 (EIE.1)
EX4 (EIE.2)
EX5 (EIE.3)
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ET2 (IE.5)
ES0 (IE.4)
ES1 (IE.6)
ENABLE
EPFI
The number of
PWDI (EIP.4)
PRIORITY
CONTROL
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
PX0 (IP.0)
PX1 (IP.2)
PT0 (IP.1)
PT1 (IP.3)
PS0 (IP.4)
PT2 (IP.5)
PS1 (IP.6)
(EIP.5)
PRTCI
N/A