DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 100

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

EFFECT OF CLOCK MODES ON TIMER OPERATION Table 7-4
SWITCHBACK
The switchback feature solves one of the most vexing dilemmas faced by power-conscious systems.
Many applications are unable to use the Stop and Idle modes because they require constant computation.
Traditionally, system designers could not reduce the operating speed below that required to process the
fastest event. This meant that system architects would be forced to operate their systems at the highest
rate of speed even when it was not required. The switchback feature allows a system to operate at a
relatively slow speed, and burst to a faster mode when required by an external event. When this feature is
enabled by setting the Switchback Enable bit, SWB, (PMR.5), a qualified interrupt or serial port reception
or transmission will cause the device to return to divide by 4 mode. A qualified interrupt is defined as an
interrupt which has occurred and been acknowledged. This means that an interrupt must be enabled and
also not blocked by a higher priority interrupt. After the event is complete, software can manually return
the device to the appropriate PMM. The following sources can trigger a switchback:
external interrupt 0/1/2/3/4/5,
serial start bit detected, Serial Port 0/1,
transmit buffer loaded, Serial Port 0/1,
watchdog timer reset,
power–on reset,
external reset.
In the case of a serial port-initiated switchback, the switchback is not generated by the associated
interrupt. This is because a device operating in PMM will not be able to correctly receive a byte of data
to generate an interrupt. Instead, a switchback is generated by a serial port reception on the falling edge
associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set. For serial
port transmissions, a switchback is generated when the serial port buffer (SBUF0;99h or SBUF1;C1h) is
loaded. This ensures the device will be operating in divide by 4 mode when the data is transmitted, and
eliminates the need for a write to the CD1, CD0 bits to exit PMM before transmitting. The switchback
feature is unaffected by the state of the serial port interrupt flags (RI_0, TI_0, RI_1, TI_1).
CD1 CD0
0
0
0
1
0
1
0
1
CYCLES PER
1024 (PMM2)
MACHINE
64 (PMM1)
Reserved
CYCLE
OSC.
4
TxM=1
OSC. CYCLES
3072
0/1/2 CLOCK
PER TIMER
192
12
TxM=0
1024
64
4
OSC. CYCLES
100 of 175
T2M=1
CLOCK,BAUD
PER TIMER 2
512
RATE GEN.
32
2
T2M=0
512
32
2
SM2=0
PORT CLOCK
OSC. CYCLES
3072
1024
PER SERIAL
12
High-Speed Microcontroller User’s Guide
MODE 0
SM2=1
1024
64
4
OSC. CYCLES PER
SMOD=0
16,348
1024
PORT CLOCK
64
MODE 2
SERIAL
SMOD=1
8192
512
32