ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 39

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

NOTES:
37. There is also a complex output mode available for 4-ch summers 1 and 3 when the cascade feature is not required. This is accomplished by
38. The cascade input of the first device in a cascade chain must be disabled.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
setting the output mode to 0x01 in the top control register and selecting the complex output mode in the main control register of channel 0 or
channel 2. This mode allows I and Q data to be clocked out in parallel at the full rate. Refer to the Main Control register for further detail.
BIT
2:1
7
6
5
4
0
3
Channel 3 Routing Routes channel 3 output to output summer 4.
Channel 3 Routing Routes channel 3 output to output summer 3.
Channel 3 Routing Routes channel 3 output to output summer 2.
Channel 3 Routing Routes channel 3 output to output summer 1.
Channel 2 Routing Routes channel 2 output to output summer 4.
Channel 2 Routing Routes channel 2 output to output summer 3.
Channel 2 Routing Routes channel 2 output to output summer 2.
Channel 2 Routing Routes channel 2 output to output summer 1.
Channel 1 Routing Routes channel 1 output to output summer 4.
Channel 1 Routing Routes channel 1 output to output summer 3
Channel 1 Routing Routes channel 1 output to output summer 2
Channel 1 Routing Routes channel 1 output to output summer 1
Channel 0 Routing Routes channel 0 output to output summer 4
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x79
FUNCTION
Sync Out Polarity
Output Enable
I Strobe Enable
I Strobe Polarity
Cascade Input Enable
Cascade Delay (1:0)
Broadcast
FUNCTION
39
Sync out polarity
Enables data out of the device. Zeroes the data when low.
Delays the 4 Ch sum to align with the cascade input summer. A cascade of 4 devices is supported.
Enables all four channels to receive current µP write access.
0 = defines a sync assertion as a transition from a logic low to a logic high.
1 = defines a sync assertion as a transition from a logic high to a logic low.
Indicates when I data is output in the muxed I/Q mode.
I strobe polarity.
0 = defines a sync assertion as a transition from a logic low to a logic high. (I out when low)
1 = defines a sync assertion as a transition from a logic high to a logic low. (I out when high)
Enables I and Q cascade data into the device. Zeroes the input buses when low. Set to zero when using
any mode other than Cascade.
00 = No Delay for master.
01 = Delay for first slave.
10 = Delay for second slave.
11 = Delay for last slave.
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x78
DESCRIPTION
TABLE 45. DEVICE CONTROL (Continued)
TABLE 46. DEVICE OUTPUT ROUTING
ISL5217
0 =
0 =
CASCADE
I
X
X
X
Q
DESCRIPTION
I
COMPLEX
1 =
1 =
OUTPUT MODE
1
X
X
X
X
X
X
X
X
X
X
Q
I
COMPLEX
Q
X
X
X
X
X
X
X
X
X
2
COMPLEX
X
X
X
X
X
X
3
IMAG, or
MUXED
REAL,
July 8, 2005
FN6004.3
X
X
X
X
X
X
X
X
X
X
X
X
X