ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 23

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

AC Electrical Specifications
NOTES:
AC Test Load Circuit
Waveforms
IIN<19:0> or QIN<19:0> Delay Time from CLK
IOUT<19:0> or QOUT<19:0> Delay Time from CLK
IIN<19:0> or QIN<19:0> Valid Time from CLK, 2X Rate
IOUT<19:0> or QOUT<19:0> Valid Time from CLK, 2X Rate
SCLKX Valid Time from CLK, SCLX = CLK
SCLKX Valid Time from CLK, SCLX = Divided CLK
ISTRB Delay Time from CLK
FSRX Delay Time from CLK
SYNCO Delay Time from CLK
P<15:0> Delay Time from CLK
P<15:0> Delay Time from A<6:0> or CS
P<15:0> Delay Time from A<6:0> or CS (RDMODE=1)
Output Rise/Fall Time (Note 7)
6. AC tests performed with C
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
Test V
RESET
CLK
IH
FIGURE 19. CLOCK AND RESET TIMING
= 3.0V, V
t
CH
t
CLK
IHC
t
CL
t
RHC
= 3.0V, V
PARAMETER
L
t
CLK
23
= 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
t
RPW
SWITCH S
†
TEST HEAD CAPACITANCE
IL
= 1 / F
= 0V, V
CLK
V
CCC
1
OPEN FOR I
OL
DUT
= 2.5 ± 5%, V
= 1.5V, V
CCSB
t
RSC
OH
C
AND I
CCIO
L
= 1.5V.
†
S
ISL5217
1
CCOP
= 3.3 ± 5%, T
SYMBOL
t
t
t
t
t
t
IQVC2X
IQVC2X
t
IQODC
SVC1X
PDAC1
A
tSVC
t
SCLKX
IQIDC
t
t
PDAC
t
SDC
PDC
t
FDC
IDC
EQUIVALENT CIRCUIT
RF
FSRX
= -40
CLK
FIGURE 20. SERIAL INTERFACE RELATIVE TIMING
I
SDX
OH
o
C to 85
±
1.5V
o
t
C (Note 6) (Continued)
SSS
MIN
2
2
2
2
2
2
2
-
-
-
-
-
-
I
t
OL
SVC
t
FDC
MAX
16
20
20
7
7
8
8
7
7
6
7
9
3
t
SHS
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
July 8, 2005
FN6004.3