ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 35

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Single Channel Indirect Registers
NOTES:
1. The contents of the last used location must be 0x800, (specified by the gain profile length).
Write access to the Gain Profile RAM:
Read access to the Gain Profile:
1. Enable the gain profile hold mode by setting bit 14 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14.
3. Load the RAM write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the RAM location
4. Wait 4 clock cycles before performing the next write to the RAM data register.
5. Repeat steps 2-4.
6. Return gain control back to the channel by disabling the gain profile hold 0x0c, bit 14.
1. Enable the gain profile hold mode by setting bit 14 of the Main Control register 0x0c.
2. Load the RAM read address and 0x8000 to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. Repeat steps 2-3.
5. Return gain control back to the channel by disabling the gain profile hold 0x0c, bit 14.
15:12
ADDRESS
INDIRECT
000 .. 07F
080 .. 0FF
100 .. 1FF
200 .. 2FF
300 .. 3FF
400 .. 407
408 .. 4FF
11:0
BIT
specified by the contents of the register at location 0x15. (Indirect address[15] =0).
of the register at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8] =’00’).
Reserved
Gain profile
FUNCTION
Page
4-F
0
0
1
2
3
4
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x000-0x07f (PAGE 0)
35
Type
R/W
R/W
R/W
R/W
Not Used.
128 location RAM that multiplies the channel gain in incremental steps at the coarse phase rate. The gain
profile is enabled by control word 0x0d[15]. The address is reset to zero on assertion of the gain profile
enable. The address is incremented by one with each change in coarse phase after assertion of the TX
enable. The address is held upon reaching the upper address used for the gain profile RAM, Gain profile
length
Bit weight 2
Maximum 0x800 = 1.0
Minimum
TABLE 39. SINGLE CHANNEL INDIRECT REGISTER MAP
Update
strobe
0x0b.
0
0x000 = 0.0
0x001 = 2-11
. 2
TABLE 40. GAIN PROFILE (15:0)
On deassertion of the TX enable the gain profile address is decremented back to zero.
-1
2
-2
Slave location
... 2
-11
ISL5217
Gain profile
Not used
Read I coefficients.
Write I and Q shaping filter coefficients
when I and Q are not equal.
Not Used.
Read Q coefficients.
Write I and Q shaping filter coefficients
when I and Q are equal.
TXENX programmed cycle values.
Not Used.
DESCRIPTION
FUNCTION
July 8, 2005
FN6004.3