ISL5217 Intersil Corporation, ISL5217 Datasheet
ISL5217
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ISL5217 Summary of contents
Page 1
... Each QPUC can create four FDM channels. Multiple QPUCs can be cascaded digitally to provide for FDM channels in multi-channel applications. The ISL5217 supports both vector and FM modulation. In vector modulation mode, the QPUC accepts 16-bit I and Q samples to generate virtually any quadrature modulation format. ...
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... Functional Block Diagram ISL5217 SERIAL SDA FM SDB INTERFACE MOD. SDC SDD I IN<15:0> Q IN<15:0> I FIFO / I IN<15:0> FIFO / Q IN<15:0> SER._PAR. MOD. TYPE <1:0> FID<31:0> SR<47:0> CHANNEL INTPL PHASES<1:0> UP PHASE OFFSET<1:0> GAIN<11:0> INTERFACE GAIN PROFILE LENGTH<6:0> AND TIMING OUTPUT_EN CARRIER PHASE<15:0> CARRIER FREQUENCY<31:0> DUALQUADMODE (CH0 AND CH2 ONLY) CLK A< ...
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... M IIN16 IIN17 IIN11 N IIN14 IIN15 IIN9 P IIN13 IIN12 IIN10 POWER PIN GROUND PIN NOTE: Thermal balls should be connected to the ground plane. 3 ISL5217 196 LdBGA TOP VIEW GND IOUT8 IOUT6 IOUT4 IOUT9 GND IOUT5 IOUT3 QOUT15 QOUT12 QOUT9 IOUT7 GND ...
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... GND - Ground, 0V MICROPROCESSOR INTERFACE AND CONTROL CLK I Input Clock. All processing in the ISL5217 occurs on the rising edge of CLK. RESET I Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, halting all processing. P<15:0> I/O Data bus. Bit 15 is the MSB. ...
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... JTAG is not utilized, this pin should be tied to ground for normal operation. As recommended in the 1149.1 standard documentation the TRST test pin should be made active soon after power-up to guarantee a known state within the TAP logic on the ISL5217. This avoids potential damage due to signal contention at the circuit’s inputs and outputs. ...
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... Functional Description The ISL5217 Quad Programmable UpConverter (QPUC) converts digital baseband data into modulated or frequency translated digital samples. The QPUC can be configured to create any quadrature amplitude shift-keyed (QASK) data modulated signal, including QPSK, BPSK, and m-ary QAM. The QPUC can also be configured to create both shaped and unfiltered FM signals ...
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... FM modulator. The FIFO can hold up to seven I /Q sample pairs. The block diagram is shown in Figure 6. 7 ISL5217 The input source to the FIFO is selected by Serial control (15). The FIFO pointer is incremented every time data is written into the FIFO. The transferring of data into the FIFO ...
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... DFF1 R E A(000) G > WR 0X11, 3:2 0X12, 9:0 0X11, 1:0 0X13, 9:0 SDA SDB SDC SDD 0X0, 15:0 A<6:0> P<15:0> 0X1, 15:0 † All Registers are clocked at CLK unless shown otherwise. 8 ISL5217 4 FIFO NEEDS MORE DATA CLOCK SYNCHRONIZATION DFF2 DFF3 DFF4 0X11 > > > SERIAL_WRITE_TO_FIFO ...
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... FIR shaping filter. The FIR shaping filter output drives the frequency control section of a quadrature NCO to produce a zero IF FM signal. These 18-bit FM 9 ISL5217 modulated quadrature samples are then up sampled in the interpolation filter to the output sample rate. The baseband modulated signal is then upconverted to the carrier frequency by the carrier NCO and mixers ...
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... Table 2 shows several examples of calculations for FIR input sample rates based on master reference clock rate, number of data samples, and interpolation rate. The data exits the shaping filters at the interpolated rate. 10 ISL5217 EXAMPLE 1 2 DEGREES/SAMPLE 3 ...
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... The default mode is 2’s complement, with 24-bit floating point mode enabled by setting control word (0x17, bit 12). 11 ISL5217 The gain through the filter is (sum of coefficients) / interpolation rate. The shaping filter contains saturation logic in the event that the final output peaks over +/- 1.0. When using quadrature modulation, saturation/overflow can occur when the input values for I and Q exceed 0 ...
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... SHIFT 0xa, bits 11:0 = Gain (11:0) MULT 12 ISL5217 Sampling NCO The Sample Rate NCO provides the SAMPLE CLK and sample clock phase information to the data input FIFO’s, the shaping filters and the interpolation filters. The input sample rate is set by the sample clock. The sample clock is ...
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... The halfband filter coefficients are -25, 0, 150, 256, 150, 0, -25 ISL5217 The output of this filter is rounded to 20-bits. The output is checked for saturation and limited if necessary. The data exits the halfband filter as a parallel I<20:0> and Q<20:0> data stream at the rate of fs*IP*2. Figure 12 shows the frequency response of the Half-Band filter ...
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... 31 CARRIER CLK 14 ISL5217 where CR(31:0) is the 32-bit frequency control word which can range from - CLK This NCO frequency range allows for spectral inversion. Given a desired carrier frequency, the value for CR(31:0) loaded into the part can be calculated by: ...
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... Complex Output Mode 3 1 (Ch. 0 and 2) NOTE: re CASout is re SUM1 + re CASinput, im CASout is im SUM1 + im CAS in. 15 ISL5217 cascade chain to select the appropriate delay. Device Control 0x78, bit 3, Cascade input enable, zeroes the cascade-in data when the port is not in use. The output of the summation is saturated to prevent roll-over ...
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... QPUC SCLKX SLAVE µP FSRX ISL5217 QPUC SDX SCLKX SLAVE µP FSRX ISL5217 QPUC SDX SCLKX SLAVE µP FSRX ISL5217 QPUC SDX FIGURE 15. CASCADED QPUCs 16 ISL5217 TABLE 8. INPUT/OUTPUT MODES IIN <19:0> 00 Input 01 Input 10 Input 11 Input 00 Output 01 Output 10 Input 11 Input I IN<19:0> CASZ MOD(20:0) † ...
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... Write Device Control 0x78, bit 0 to set the broadcast bit if writing to multiple channels. Set to 0 when writing to a single channel. 3. Write all remaining registers sequentially. 4. Load all filter and gain coefficients. 17 ISL5217 5. Repeat steps 2-4 for all channels. 6. Write control word 0x0c to the final configuration values. RDMODE RD WR A< ...
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... RAM data register. 6. Repeat steps 2-5. 7. Return RAM control back to the channel by disabling the µP hold mode. 18 ISL5217 Write Access to the Coefficient RAMs When I Equal Q 1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c. 2. Load the RAM data to location 0x14 with the coefficient. ...
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... There are two types of resets, a hard reset and a soft reset. A hard reset can occur by asserting the input pin RESET ISL5217 by the µP issuing a reset command to the top control register 0x7F, bit 1. A hard reset affects the entire device, leaving the QPUC in an idle state awaiting configuration ...
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... Power-up Sequencing The ISL5217 core and I/O blocks are isolated by structures which may become forward biased if the supply voltages are 20 ISL5217 not at specified levels ...
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... C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major A process or design changes. 21 ISL5217 Thermal Information Thermal Resistance (Typical, Notes 1, 3) +0.5V 196 Lead BGA Package ...
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... Hold Time SDX from SCLKX IOUT<19:0> or QOUT<19:0> Enable Time from OUTEN<1:0> (Note 7) IIN<19:0> or QIN<19:0> Enable Time from CLK (Note 7) IOUT<19:0> or QOUT<19:0> Disable Time from OUTEN<1:0> (Note 7) IIN<19:0> or QIN<19:0> Disable Time from CLK (Note 7) 22 ISL5217 V = 2.5 ± 5 3.3 ± 5 -40 CCC CCIO ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. AC Test Load Circuit SWITCH S † TEST HEAD CAPACITANCE Waveforms t CLK CLK CLK t RHC t RPW RESET FIGURE 19. CLOCK AND RESET TIMING 23 ISL5217 V = 2.5 ± 5 3.3 ± 5 -40 CCC CCIO A SYMBOL t IQIDC t IQODC t IQVC2X t IQVC2X t SVC1X tSVC t IDC t ...
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... CLK IIN<19:0>, QIN<19:0>, IOUT<19:0>, QOUT<19:0> FIGURE 23. MUXED OUTPUT TIMING t RD WPWL t WPWH VALID A<6:0> t VALID P<15:0> FIGURE 25. MICROPROCESSOR WRITE TIMING (RDMODE = 0) 24 ISL5217 t IQIHC VALID IIN<19:0>, QIN<19:0> OUTEN<1:0> USC, TSC t t UHC, THC IOUT<19:0>, QOUT<19:0> CLK t IQVC2X SCLKX RD (RD/WR) ...
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... Decode indirect address <9:8> to determine page, (3 used). 15. Indirect address<14:10> are not used. 16. Indirect address<15> determines access type. 1=read; 0=write. 25 ISL5217 RD (RD/WR) WR (DS) A<6:0> t PDR VALID P<15:0> FIGURE 28. MICROPROCESSOR READ TIMING (RDMODE = 1) TABLE 10. ISL5217 MEMORY MAP DEVICE MEMORY MAP Channel 0 Undefined Channel 1 Undefined Channel 2 Undefined Channel 3 Device control CS VALID t ...
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... Channel summary fault is the logical or’ing of channel status <10:7,3>. 18. Clear fault by writing “1” to each summary fault bit (15:11). 19. Channel summary status is cleared as well as the Channel status word. 20. Output summary fault clears top status bits <9:0>. 26 ISL5217 TABLE 11. DEVICE CONTROL REGISTER MAP SLAVE LOCATION QC µP Intf Device Control < ...
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... R/W 18:1F 27 ISL5217 TABLE 14. DEVICE IMMEDIATE ACTION TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x7f TABLE 15. SINGLE CHANNEL DIRECT REGISTER MAP SLAVE LOCATION X FIFO I Channel Input or FM <15:0>. X FIFO Q Channel input <15:0>. Sample NCO Fixed Integer divider <31:16> MSW. Sample NCO Fixed Integer divider <15:0> LSW. ...
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... The sample rate is computed by the formula: SF (47:0) = INT [( CLK ) * 2 48 NOTE: Writing to the LSW generates the update strobe to load the slave configuration reg when in the immediate mode. 28 ISL5217 TABLE 16. I CHANNEL INPUT OR FM (15:0) TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x00 DESCRIPTION TABLE 17 ...
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... TXENX as input to the channel. 6:0 Gain Profile Length Set to the upper address used for the gain profile RAM. 29 ISL5217 TABLE 23. CARRIER PHASE OFFSET (15:0) TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x07 TABLE 24. CARRIER FREQUENCY (31:16) MSW TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x08 CF(31:16) is loaded in this address ...
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... FIFO overflow channel reset disabled Enable Rising edge flushes data RAM, (16 clks) and updates configuration slave registers as determined by the update mask. High level allows serial requests to occur. Low level inhibits additional serial data requests, (assertion TX frame strobe). 30 ISL5217 TABLE 28. MAIN CONTROL DESCRIPTION ...
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... Modulation type(1: QASK - PSK or QAM modulation post-filtering - Analog FM modulation. Filtering after FM modulation (baseband filtering provided before ISL5217). In this mode both I and Q filters are used pre-filtering - FSK, GMSK modulation. Filtering before FM modulation. In this mode, only the I filter is used Invalid state. ...
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... Serial CLK Polarity Serial clk polarity defines an assertion as a transition from a logic low to a logic high 1 = defines an assertion as a transition from a logic high to a logic low 32 ISL5217 TABLE 30. UPDATE MASK (Continued) TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0e 1 = Update Update. TABLE 31. IMMEDIATE ACTION TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0f TABLE 32 ...
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... FUNCTION 15:10 Reserved Not Used. 9:0 Q Time Slot (9:0) The assertion of the Frame strobe. The carryout determines when a valid Q symbol has been shifted in. 33 ISL5217 TABLE 33. SERIAL CONTROL (13:0) DESCRIPTION 1101 = clk/28 1110 = clk/30 1111 = clk/32 TABLE 34 SERIAL TIME SLOT DESCRIPTION I - SERIAL TIME SLOT bit counter clocked at the serial clock rate ...
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... The status register is cleared by writing to the Top status register. 35. Detection of FIFO overflow puts the channel in the off-line mode. 36. The Channel flushed status is be asserted 24 sample clocks after entering the off-line mode. 34 ISL5217 TABLE 35 SERIAL TIME SLOT (Continued) TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x13 DESCRIPTION TABLE 36 ...
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... Indirect address[9:8] =’00’). 3. Wait 4 clock cycles before performing the next write to the RAM address register. 4. Repeat steps 2-3. 5. Return gain control back to the channel by disabling the gain profile hold 0x0c, bit 14. 35 ISL5217 TABLE 39. SINGLE CHANNEL INDIRECT REGISTER MAP Update strobe Slave location ...
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... Wait 4 clock cycles between all of the above writes before performing the next write to the Ram address register. 4. Repeat steps 2-3. 5. Return RAM control back to the channel by disabling the µP hold mode. 36 ISL5217 TABLE 41. I AND Q CHANNEL COEFFICIENTS (15:0) DESCRIPTION ...
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... Wait 4 clock cycles before performing the next write to the address register. 4. Return control back to the channel by disabling the µP hold mode. 37 ISL5217 TABLE 42. I AND Q CHANNEL COEFFICIENTS (15:0) DESCRIPTION TABLE 43. TXENX CONTROL DESCRIPTION ...
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... Four channel I data out at 104MHz 20 Four channel Q data out at 104MHz 20 Four channel muxed I/Q data out at 52MHz 20) 38 ISL5217 TABLE 44. TEST CONTROL (15:0) TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x17 FSRX and SCLKX, from default, turn off synchronously to CLK. Set enable FSRX and SCLKX signals to be shut off on the boundary of SCLKX ...
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... Channel 1 Routing Routes channel 1 output to output summer 3 5 Channel 1 Routing Routes channel 1 output to output summer 2 4 Channel 1 Routing Routes channel 1 output to output summer 1 3 Channel 0 Routing Routes channel 0 output to output summer 4 39 ISL5217 TABLE 45. DEVICE CONTROL (Continued) TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x78 DESCRIPTION TABLE 46 ...
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... ISL5217 TABLE 46. DEVICE OUTPUT ROUTING (Continued) DESCRIPTION CASCADE X BIT CH ASSIGNMENT TO OUTPUT SUMMERS 15:12 Summer 4, Summer 3, Summer 2, Summer 1. 11:8 Summer 4, Summer 3, Summer 2, Summer 1. 7:4 Summer 4, Summer 3, Summer 2, Summer 1. 3:0 Summer 4, Summer 3, Summer 2, Summer 1. TABLE 48. OUTPUT MODES IIN IIN QIN QIN ...
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... IP7 7 23 IP8 8 24 IP9 9 25 IP10 10 26 IP11 11 27 IP12 12 28 IP13 13 29 IP14 14 30 IP15 15 31 REVISION NUMBER REVISION DATE 6004.2 February 20, 2003 41 ISL5217 TABLE 49. COEFFICIENT ADDRESSES DS[n-2] DS[n-3] DS[n-4] ... ... ... ... ... ... ... ... ...
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... Any such changes will be backwards compatible to the existing device, such that the recommended work-arounds will not affect the operation of the device in existing designs. 42 ISL5217 ALT_WR WR_PAD RDMODE ALT_RD RD_PAD ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 43 ISL5217 A V196.15x15 196 BALL PLASTIC BALL GRID ARRAY PACKAGE ...