ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 25

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Waveforms
Programming Information
FIGURE 27. MICROPROCESSOR READ TIMING (RDMODE = 0)
NOTES:
10. All configuration registers have a master/slave architecture. The master registers are clocked by WR. The slave registers are clocked by CLK.
11. The master registers are writable and cleared by a hard reset. All master registers are located in the SC µP block.
12. The slave registers are readable and cleared by either a hard or soft reset. Refer to the table to determine location of slave registers.
13. Partition indirect address space into pages of 256 words.
14. Decode indirect address <9:8> to determine page, (3 used).
15. Indirect address<14:10> are not used.
16. Indirect address<15> determines access type. 1=read; 0=write.
8. Consecutive accesses to the same address require a 4 clock synchronized update to occur before beginning the next accesses.
9. Different direct address locations can be accessed without having to wait for a 4 clock synchronized update to occur.
P<15:0>
A<6:0>
RD
WR
CS
(000 0000) - (001 0111)
(001 1000) - (001 1111)
(010 0000) - (011 0111)
(011 1000) - (011 1111)
(100 0000) - (101 0111)
(101 1000) - (101 1111)
(110 0000) - (111 0111)
(111 1000) - (111 1111)
ADDRESS(6:0)
0x00 - 0x17
0x18 - 0x1f
0x38 - 0x3f
0x58 - 0x5f
0x20-0x37
0x40-0x57
0x60-0x77
0x78-0x7f
(Continued)
VALID
t
PDAC
t
PER
25
VALID
Channel 0
Undefined
Channel 1
Undefined
Channel 2
Undefined
Channel 3
Device control
TABLE 10. ISL5217 MEMORY MAP
t
PDR
ISL5217
FIGURE 28. MICROPROCESSOR READ TIMING (RDMODE = 1)
RD (RD/WR)
WR (DS)
P<15:0>
A<6:0>
DEVICE MEMORY MAP
CS
t
PEWR1
t
PDAC1
VALID
VALID
July 8, 2005
t
PDWR1
FN6004.3