ISL5217_05 INTERSIL [Intersil Corporation], ISL5217_05 Datasheet - Page 18

• Manufacturer Part Number: ISL5217_05
• Description: Quad Programmable Up Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Gain Profile RAM Read/Write Procedure
Write Access to the Gain Profile RAM
Read Access to the Gain Profile
Coefficients RAM Read/Write Procedure
(16-bit 2’s Complement Format)
The RAM address used for the I and Q coefficient RAM
depends on the filter. Indirect page 3 is used when the
coefficients are equal. When the coefficients are not equal
indirect page 1 is used.
Write Access to the Coefficient RAMs When I Not
Equal Q
1. Enable the gain profile hold mode by setting bit 14 of the
2. Load the RAM data to location 0x14.
3. Load the RAM write address to location 0x15. A write
4. Wait 4 clock cycles before performing the next write to the
5. Repeat steps 2-4.
6. Return gain control back to the channel by disabling the
1. Enable the gain profile hold mode by setting bit 14 of the
2. Load the RAM read address and 0x8000 to location 0x15.
3. Wait 4 clock cycles before performing the next write to the
4. Repeat steps 2-3.
5. Return gain control back to the channel by disabling the
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM data to location 0x14 with the Q
3. Load the RAM data to location 0x14 with the I coefficient.
4. Load the RAM write address to location 0x15. A write
5. Wait 4 clock cycles before performing the next write to the
6. Repeat steps 2-5.
7. Return RAM control back to the channel by disabling the
Main Control register 0x0c.
strobe transfers the contents of the register at location
0x14 into the RAM location specified by the contents of
the register at location 0x15. (Indirect address[15] =0).
RAM data register.
gain profile hold 0x0c, bit 14.
Main Control register 0x0c.
A read strobe transfers the contents of the RAM location
specified by the contents of the register at location 0x15
onto the read bus. (Indirect address[15] =1, Indirect
address[9:8] =’00’).
RAM address register.
gain profile hold 0x0c, bit 14.
Control register 0x0c.
coefficient.
strobe transfers the contents of the register at location
0x14 into the RAM location specified by the contents of
the register at location 0x15. (Indirect address[15] =0,
Indirect address[9:8] =’01’).
RAM data register.
µP hold mode.
18
ISL5217
Write Access to the Coefficient RAMs When I
Equal Q
Read Access to the I Coefficient RAM
Read Access to the Q Coefficient RAM
Coefficients RAM Read/Write Procedure
(24-bit Floating Point Format)
The 24-bit floating point mode must be enabled by setting bit
12 of control word 0x17. The I and Q coefficients must be
loaded separately in this mode.
Write access to the Coefficient RAMs
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM data to location 0x14 with the coefficient.
3. Load the RAM write address to location 0x15. A write
4. Wait 4 clock cycles before performing the next write to the
5. Repeat steps 2-4.
6. Return RAM control back to the channel by disabling the
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM read address and 0x8100 to location 0x15.
3. Wait 4 clock cycles before performing the next write to the
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM read address and 0x8200 to location 0x15.
3. Wait 4 clock cycles before performing the next write to the
4. After all data has been loaded, return RAM control back
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM data to location 0x14 with the iCoef<3:0>,
Control register 0x0c.
strobe transfers the contents of the register at location
0x14 into the RAM location specified by the contents of
the register at location 0x15. (Indirect address[15] =0,
Indirect address[9:8] =’11’).
RAM data register.
µP hold mode.
Control register 0x0c.
A read strobe transfers the contents of the RAM location
specified by the contents of the register at location 0x15
onto the read bus. (Indirect address[15] =1, Indirect
address[9:8] =’01’).
Ram address register.
µP hold mode.
Control register 0x0c.
A read strobe transfers the contents of the RAM location
specified by the contents of the register at location 0x15
onto the read bus. (Indirect address[15] =1, Indirect
address[9:8] =’10’).
RAM address register.
to the channel by disabling the µP hold mode.
Control register 0x0c and bit 12 of the Test Control
register 0x17.
iShift<3:0>, qCoef<3:0>, qShift<3:0>.
July 8, 2005
FN6004.3