PCF2127AT/1 NXP [NXP Semiconductors], PCF2127AT/1 Datasheet - Page 59

• Manufacturer Part Number: PCF2127AT/1
• Description: Integrated RTC, TCXO and quartz crystal
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF2127A_2
Product data sheet
Fig 43. Bus protocol, reading from registers
S
S
1
1
0
0
slave address
slave address
1
1
Table 59.
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge bit (A) refer to the I
characteristics table
either a STOP condition or the START condition of the next data transfer.
Bit
Fig 42. Bus protocol, writing to registers
0
0
S
0
0
1
0
0
Slave address
7
MSB
1
0
I
2
C slave address byte
slave address
1
1
1
write bit
read bit
from PCF2127A
from PCF2127A
All information provided in this document is subject to legal disclaimers.
acknowledge
acknowledge
0
1
0
6
0
(Table
A
A
0
Rev. 02 — 7 May 2010
0
0 to n data bytes
register address
64). In the write mode a data transfer is terminated by sending
DATA BYTE
00h to 1Dh
1
write bit
5
1
from PCF2127A
acknowledge
0
2
C-bus specification
A
from PCF2127A
acknowledge
acknowledge
from master
4
0
register address
A
A
00h to 1Dh
STOP
Integrated RTC, TCXO and quartz crystal
P
LAST DATA BYTE
3
0
from PCF2127A
acknowledge
Ref. 13 “UM10204”
A
no acknowledge
2
0
A
data bytes
0 to n
PCF2127A
P
1
1
© NXP B.V. 2010. All rights reserved.
read register
data
set register
address
and the
from PCF2127A
acknowledge
001aaj721
A
0
LSB
R/W
START/
STOP
001aaj719
P/S
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