PCF2127AT/1 NXP [NXP Semiconductors], PCF2127AT/1 Datasheet - Page 27

• Manufacturer Part Number: PCF2127AT/1
• Description: Integrated RTC, TCXO and quartz crystal
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF2127A_2
Product data sheet
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic
1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in
Figure
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
Fig 15. Power-On Reset (POR) system
Fig 16. Power-On Reset Override (PORO) sequence, valid for both I
reset override
SDA/CE
16. All timings shown are required minimum.
SCL
power up
8 ms
All information provided in this document is subject to legal disclaimers.
SDA/CE
SCL
Rev. 02 — 7 May 2010
OSCILLATOR
POR_OVRD
OVERRIDE
RESET
CLEAR
0 = override inactive
1 = override active
0 = clear override mode
1 = override possible
0 = stopped, 1 = running
minimum 500 ns
osc stopped
Integrated RTC, TCXO and quartz crystal
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reset
PCF2127A
2
C-bus and SPI-bus
minimum 2000 ns
© NXP B.V. 2010. All rights reserved.
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