PCF2127AT/1 NXP [NXP Semiconductors], PCF2127AT/1 Datasheet - Page 57

• Manufacturer Part Number: PCF2127AT/1
• Description: Integrated RTC, TCXO and quartz crystal
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF2127A_2
Product data sheet
9.2.1 Bit transfer
9.2.2 START and STOP conditions
9.2.3 System configuration
9.2 I
The I
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition S. A
LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP
condition P (see
Remark: For the PCF2127A a repeated START is not allowed. Therefore a STOP has to
be released before the next START.
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves.
The PCF2127A can act as a slave transmitter and a slave receiver.
2
Fig 38. Bit transfer
Fig 39. Definition of START and STOP conditions
C-bus interface
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
Figure
SDA
SCL
S
39).
Rev. 02 — 7 May 2010
data valid
data line
stable;
Figure
38).
Integrated RTC, TCXO and quartz crystal
allowed
change
of data
STOP condition
PCF2127A
mbc621
P
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
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