CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 48

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Comments
Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits
[3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 19-1, the SIE will change the endpoint Mode Bits [3:0]
to NAK IN-Status OUT mode (1110) after ACK’ing a valid status stage OUT token. The firmware needs to update the mode for
the SIE to respond appropriately. See Table 18-1 for more details on what modes will be changed by the SIE. A disabled endpoint
will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). Firmware normally enables
the endpoint mode after a SetConfiguration request.
Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token.
The control endpoint has three status bits for identifying the token type received (SETUP, IN, or OUT), but the endpoint must be
placed in the correct mode to function as such. Non-Control endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which
NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110.
The response of the SIE can be summarized as follows:
Table 20-2. Decode Table for Table 20-3: “Details of Modes for Differing Traffic Conditions”
1. The SIE will only respond to valid transactions, and will ignore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs
3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa versa.
5. The IN and OUT PID status is updated at the end of a transaction.
6. The SETUP PID status is updated at the beginning of the Data packet phase.
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
3
Endpoint Mode
encoding
Legend:
during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete. This represents about a 1- s window in which the CPU is locked
from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that
the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of
the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to
make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This
read will of course unlock the register. So care must be taken not to overwrite the register elsewhere.
2
1
0
Received Token
(SETUP/IN/OUT)
Token
TX: transmit
RX: receive
x: don’t care
Properties of
Incoming Packets
count
The number of received bytes
available for Control endpoint only
buffer
The quality status of the DMA buffer
UC : unchanged
TX0:Transmit 0 length packet
dval
The validity of the received data
Changes to the Internal Register made by the SIE on receiving an incoming
packet from the host
DTOG
Data0/1 (bit7 Figure 17-4)
DVAL
Data Valid (bit 6, Figure 17-4)
COUNT
Byte Count (bits 0..5, Figure 17-4)
Setup
PID Status Bits
(Bit[7..5], Figure
17-2)
In
Out
ACK
Acknowledge phase completed
3
CY7C66013C
CY7C66113C
2 1 0 Response
Endpoint Mode bits
Changed by the SIE
Page 48 of 61
SIE’s Response
to the Host
Interrupt
Int
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