CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 31

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
15.0
Bit 0: Run
Bit 1: Reserved
Bit 2: Interrupt Enable Sense
Bit 3: Suspend
Bit 4: Power-on Reset
Bit 5: USB Bus Reset Interrupt
Bit 6: WDR
Bit 7: IRQ Pending
During power-up, the Processor Status and Control Register is set to 00010001, which indicates a POR (bit 4 set) has occurred
and no interrupts are pending (bit 7 clear). During the 96 ms suspend at start-up (explained in Section 7.1), a WDR also occurs
unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend interval, firmware
reads 01010001 from the Status and Control Register after power-up. Normally, the POR bit should be cleared so a subsequent
WDR can be clearly identified. If an upstream bus reset is received before firmware examines this register, the Bus Reset bit may
also be set.
During a WDR, the Processor Status and Control Register is set to 01XX0001, which indicates a WDR (bit 6 set) has occurred
and no interrupts are pending (bit 7 clear). The WDR does not effect the state of the POR and the Bus Reset Interrupt bits.
16.0
Interrupts are generated by the GPIO/DAC pins, the internal timers, I
on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point
Interrupt Enable Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position.
Processor Status and Control
Bit #
Bit Name
Read/Write
Reset
This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor
remains halted until an appropriate reset occurs (power-on or Watchdog). This bit should normally be written as a ‘1.’
Bit 1 is reserved and must be written as a zero.
This bit indicates whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero
or one to this bit position has no effect on interrupts. A ‘0’ indicates that interrupts are masked off and a ‘1’ indicates that
the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (Figure 16-1)
and USB End Point Interrupt Enable Register (Figure 16-2). Instructions DI, EI, and RETI manipulate the state of this bit.
Writing a ‘1’ to the Suspend bit halts the processor and cause the microcontroller to enter the suspend mode that signifi-
cantly reduces power consumption. A pending, enabled interrupt or USB bus activity causes the device to come out of
suspend. After coming out of suspend, the device resumes firmware execution at the instruction following the IOWR which
put the part into suspend. An IOWR attempting to put the part into suspend is ignored if USB bus activity is present. See
Section 8.0 for more details on suspend mode operation.
The Power-on Reset is set to ‘1’ during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to
determine whether a reset was caused by a power-on condition or a Watchdog timeout. A POR event may be followed by
a WDR before firmware begins executing, as explained below.
The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detected on receiving a USB Bus Reset signal on the
upstream port. The USB Bus Reset signal is a single-ended zero (SE0) that lasts from 12 to 16 s. An SE0 is defined as
the condition in which both the D+ line and the D– line are LOW at the same time.
The WDR is set during a reset initiated by the WDT. This indicates the WDT went for more than t
between Watchdog clears. This can occur with a POR event, as noted below.
The IRQ pending, when set, indicates that one or more of the interrupts has been recognized as active. An interrupt remains
pending until its interrupt enable bit is set (Figure 16-1, Figure 16-2) and interrupts are globally enabled. At that point, the
internal interrupt handling sequence clears this bit until another interrupt is detected as pending.
Processor Status and Control Register
Interrupts
7
IRQ
Pending
R
0
6
Reset
R/W
0
Watchdog
Figure 15-1. Processor Status and Control Register
5
USB Bus Reset
Interrupt
R/W
0
4
Power-On
Reset
R/W
1
2
C-compatible or HAPI operation, the internal USB hub, or
3
R/W
0
Suspend
2
Interrupt
Enable Sense
R
0
1
R/W
0
Reserved
CY7C66013C
WATCH
CY7C66113C
(8 ms minimum)
Page 31 of 61
ADDRESS 0xFF
0
Run
R/W
1
[+] Feedback
[+] Feedback