CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 42

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Bit 3: Bus Activity
Bits 4 and 5: D– Upstream and D+ Upstream
Bit 6: Endpoint Mode
Bit 7: Endpoint Size
The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2.
19.0
The CY7C66x13C SIE supports operation as a single device or a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint function.
19.1
The USB Controller provides two USB Device Address Registers: A (addressed at 0x10)and B (addressed at 0x40). Upon reset
and under default conditions, Device A has three endpoints and Device B has two endpoints. The USB Device Address Register
contents are cleared during a reset, setting the USB device addresses to zero and disabling these addresses. Figure 19-1 shows
the format of the USB Address Registers.
USB Device Address (Device A, B)
Bits[6..0]: Device Address
Bit 7: Device Address Enable
19.2
The CY7C66x13C controller supports up to two addresses and five endpoints for communication with the host. The configuration
of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (see Figure 18-10).
Bit 7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in
Table 19-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).
Table 19-1. Memory Allocation for Endpoints
Endpoints) & B (2 Endpoints)
Bit #
Bit Name
Read/Write
Reset
Label
EPB1
EPB0
EPA2
EPA1
EPA0
Two USB Addresses: A (3
This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while writing
a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.
This bit used to configure the number of USB endpoints. See Section 19.2 for a detailed description.
This bit used to configure the number of USB endpoints. See Section 19.2 for a detailed description.
Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host.
Must be set by firmware before the SIE can respond to USB traffic to the Device Address.
USB Device Addresses
USB Device Endpoints
USB SIE Operation
Address
0xD8
0xE0
0xE8
Start
0xF0
0xF8
[0,0]
7
Device
Address
Enable
R/W
0
Size
8
8
8
8
8
6
Device
Address
Bit 6
R/W
0
Endpoints) &B (2 Endpoints)
Label
EPB0
EPB1
EPA0
EPA1
EPA2
Two USB Addresses: A (3
USB Status And Control Register (0x1F) Bits [7, 6]
Figure 19-1. USB Device Address Registers
5
Device
Address
Bit 5
R/W
0
Address
0xC0
Start
0xA8
0xB0
0xB8
0xE0
[1,0]
4
Device
Address
Bit 4
R/W
0
Size
32
32
8
8
8
Label
EPA4
EPA3
EPA2
EPA1
EPA0
One USB Address:
3
Device
Address
Bit 3
R/W
0
A (5 Endpoints)
Address
Start
0xD8
0xE0
0xE8
0xF0
0xF8
[0,1]
2
Device
Address
Bit 2
R/W
0
Size
8
8
8
8
8
ADDRESSES
Label
EPA3
EPA4
EPA0
EPA1
EPA2
1
Device
Address
Bit 1
R/W
0
One USB Address:
A (5 Endpoints)
CY7C66013C
CY7C66113C
Address
Start
0xA8
0xB0
0xB8
0xC0
0xE0
[1,1]
0x10(A) and 0x40(B)
Page 42 of 61
0
Device
Address
Bit 0
R/W
0
Size
32
32
8
8
8
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