CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 43

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a
delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
19.3
All USB devices are required to have a control endpoint 0 (EPA0 and EPB0) that is used to initialize and control each USB address.
Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses. Endpoint
0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or
OUT endpoints.
The endpoint mode registers are cleared during reset. When USB Status And Control Register Bits [6,7] are set to [0,0] or [1,0],
the endpoint 0 EPA0 and EPB0 mode registers use the format shown in Figure 19-2.
USB Device Endpoint Zero Mode (A0, B0)
Bits[3..0]: Mode
Bit 4: ACK
Bit 5: Endpoint 0 OUT Received
Bit 6: Endpoint 0 IN Received
Bit 7: Endpoint 0 SETUP Received
Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the mode registers of other endpoints.
Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies
that the contents have changed as desired, and that the SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 19-1 for the appropriate endpoint zero
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 18-1.
Additional information on the mode bits can be found in Table 20-2 and Table 20-1.
Note: The SIE offers an “Ack out - Status in” mode and not an “Ack out - Nak in” mode. Therefore, if following the status stage
of a Control Write transfer a USB host were to immediately start the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
Bit #
Bit Name
Read/Write
Reset
These sets the mode which control how the control endpoint responds to traffic.
This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
1 = Token received is an OUT token. 0 = Token received is not an OUT token. This bit is set by the SIE to report the type
of token received by the corresponding device address is an OUT token. The bit must be cleared by firmware as part of
the USB processing.
1 = Token received is an IN token. 0 = Token received is not an IN token. This bit is set by the SIE to report the type of
token received by the corresponding device address is an IN token. The bit must be cleared by firmware as part of the USB
processing.
1 = Token received is a SETUP token. 0 = Token received is not a SETUP token. This bit is set ONLY by the SIE to report
the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will
clear it (set it to 0). The bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start
of the ACK packet returned by the SIE. The CPU should not clear this bit during this interval, and subsequently, until the
CPU first does an IORD to this endpoint 0 mode register. The bit must be cleared by firmware as part of the USB processing.
Note: In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as
non-control endpoint 3, and has the format for non-control endpoints shown in Figure 19-3.
USB Control Endpoint Mode Registers
7
Endpoint 0 SETUP
Received
R/W
0
6
Endpoint 0 IN
Received
R/W
0
Figure 19-2. USB Endpoint 0 Mode Registers
5
Endpoint 0 OUT
Received
R/W
0
4
ACK
R/W
0
3
Mode Bit 3
R/W
0
2
Mode Bit 2
R/W
0
ADDRESSES
Mode Bit 1
1
R/W
0
CY7C66013C
CY7C66113C
0x12(A0) and 0x42(B0)
Page 43 of 61
0
Mode Bit 0
R/W
0
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