CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 4

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Figure 3-1. CY7C66113C 56-pin QFN Pin Assignment .......................................................................11
Figure 3-2. CY7C66113C DIE ..............................................................................................................12
Figure 5-1. Program Memory Space with Interrupt Vector Table .........................................................18
Figure 6-1. Clock Oscillator On-Chip Circuit ........................................................................................20
Figure 7-1. Watchdog Reset ................................................................................................................21
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................22
Figure 9-2. Port 0 Data ........................................................................................................................23
Figure 9-3. Port1 Data .........................................................................................................................23
Figure 9-4. Port 2 Data ........................................................................................................................23
Figure 9-5. Port 3 Data ........................................................................................................................23
Figure 9-6. GPIO Configuration Register .............................................................................................23
Figure 9-7. Port 0 Interrupt Enable .......................................................................................................24
Figure 9-8. Port 1 Interrupt Enable .......................................................................................................25
Figure 9-9. Port 2 Interrupt Enable .......................................................................................................25
Figure 9-10. Port 3 Interrupt Enable .....................................................................................................25
Figure 10-1. Block Diagram of a DAC Pin ............................................................................................25
Figure 10-2. DAC Port Data .................................................................................................................26
Figure 10-3. DAC Sink Register ...........................................................................................................26
Figure 10-4. DAC Port Interrupt Enable ...............................................................................................26
Figure 10-5. DAC Port Interrupt Polarity ..............................................................................................26
Figure 11-3. Timer Block Diagram .......................................................................................................27
Figure 11-1. Timer LSB Register .........................................................................................................27
Figure 11-2. Timer MSB Register ........................................................................................................27
Figure 12-1. HAPI/I
Figure 13-1. I
Figure 13-2. I
Figure 15-1. Processor Status and Control Register ...........................................................................31
Figure 16-1. Global Interrupt Enable Register .....................................................................................32
Figure 16-2. USB Endpoint Interrupt Enable Register .........................................................................32
Figure 16-3. Interrupt Controller Function Diagram .............................................................................33
Figure 16-4. GPIO Interrupt Structure ..................................................................................................35
Figure 18-1. Hub Ports Connect Status ...............................................................................................38
Figure 18-2. Hub Ports Speed .............................................................................................................38
Figure 18-3. Hub Ports Enable Register ..............................................................................................38
Figure 18-4. Hub Downstream Ports Control Register .........................................................................39
Figure 18-5. Hub Ports Force Low Register .........................................................................................39
Figure 18-6. Hub Ports SE0 Status Register .......................................................................................39
Figure 18-7. Hub Ports Data Register ..................................................................................................40
Figure 18-8. Hub Ports Suspend Register ...........................................................................................40
Figure 18-9. Hub Ports Resume Status Register .................................................................................40
Figure 18-10. USB Status and Control Register ..................................................................................41
Figure 19-1. USB Device Address Registers .......................................................................................42
Figure 19-2. USB Endpoint 0 Mode Registers .....................................................................................43
Figure 19-3. USB Non-Control Endpoint Mode Registers ....................................................................44
Figure 19-4. USB Endpoint Counter Registers ....................................................................................44
Figure 19-5. Token/Data Packet Flow Diagram ...................................................................................46
Figure 22-1. Sample Schematic ...........................................................................................................53
Figure 25-1. Clock Timing ....................................................................................................................56
Figure 25-2. USB Data Signal Timing ..................................................................................................56
Figure 25-3. HAPI Read by External Interface from USB Microcontroller ............................................56
Figure 25-4. HAPI Write by External Device to USB Microcontroller ...................................................57
Figure 28-1. Cross-section of the Area Underneath the QFN Package ...............................................60
Figure 28-2. Plot of the Solder Mask (White Area) ..............................................................................60
2
2
C Data Register .............................................................................................................28
C Status and Control Register .......................................................................................28
2
C Configuration Register ......................................................................................27
LIST OF FIGURES
CY7C66013C
CY7C66113C
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