CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 27

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Bit [7..0]: Polarity bit x (x= 0..7)
11.0
The 12-bit timer operates with a 1- s tick, provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
8 bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.
Bit [7:0]: Timer lower eight bits
Timer MSB
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved
12.0
Internal hardware supports communication with external devices through two interfaces: a two-wire I
for 1, 2, or 3 byte transfers. The I
common configuration register (see Figure 12-1)
I
Note:
Timer LSB
2
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
3.
C Configuration
1= Selects positive polarity (rising edge) that causes an interrupt (if enabled);
0 = Selects negative polarity (falling edge) that causes an interrupt (if enabled).
I
2
C-compatible function must be separately enabled, as described in Section 13.0.
12-bit Free-running Timer
I
2
C and HAPI Configuration Register
7
Timer Bit 7
R
0
7
Reserved
-
0
7
I
R/W
0
2
C Position
11
L
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
10 9
L2
6
Timer Bit 6
R
0
6
Reserved
-
0
6
Reserved
-
0
L1 L0
2
C-compatible and HAPI functions, discussed in detail in Sections 13.0 and 14.0, share a
8
Figure 12-1. HAPI/I
7
5
Timer Bit 5
R
0
5
Reserved
-
0
5
LEMPTY
Polarity
R/W
0
Figure 11-3. Timer Block Diagram
Figure 11-1. Timer LSB Register
6
Figure 11-2.
[3]
. All bits of this register are cleared on reset.
5
4
Timer Bit 4
R
0
4
Reserved
-
0
4
DRDY
Polarity
R/W
0
4
2
C Configuration Register
Timer MSB Register
3
2
3
Timer Bit 3
R
0
3
Timer Bit 11
R
0
3
Latch
Empty
R
0
1
0
8
2
Timer Bit 2
R
0
2
Timer Bit 10
R
0
2
Data
Ready
R
0
1.024-ms interrupt
128- s interrupt
1-MHz clock
To Timer Registers
1
Timer Bit 1
R
0
1
Timer Bit 9
R
0
1
HAPI Port
Width Bit 1
R/W
0
2
C-compatible, and a HAPI
CY7C66013C
CY7C66113C
Page 27 of 61
0
Timer Bit 0
R
0
0
Timer Bit 8
R
0
0
HAPI Port
Width Bit 0
R/W
0
ADDRESS 0x24
ADDRESS 0x25
ADDRESS 0x09
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