CY7C1470V25_12 CYPRESS [Cypress Semiconductor], CY7C1470V25_12 Datasheet - Page 9

• Manufacturer Part Number: CY7C1470V25_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 38-05290 Rev. *O
A
BW
BW
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
MODE
TDO
TDI
Pin Name
0
, A
1
2
3
s
a
c
e
g
, BW
, BW
, BW
, BW
X
1
, A
b
d
f
h
,
,
,
asynchronous
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
JTAG serial
JTAG serial
I/O Type
output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
clock
input
I/O-
I/O-
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK. BW
and DQP
BW
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
Advance/load input used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
sequences, DQP
DQP
by BW
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
g
d
controls DQ
is controlled by BW
g,
3
3
2
DQP
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
c
, BW
h
is controlled by BW
d
controls DQ
g
a
and DQP
is controlled by BW
d
, DQP
a
g,
controls DQ
d
BW
and DQP
e
h
h
is controlled by BW
controls DQ
.
a
, DQP
d
a
, BW
and DQP
Pin Description
b
e
h
is controlled by BW
controls DQ
and DQP
a
, BW
e,
DQP
b
h
controls DQ
.
e
f
and DQP
is controlled by BW
b
, DQP
b
e,
and DQP
BW
c
is controlled by BW
f
controls DQ
CY7C1470V25
CY7C1472V25
CY7C1474V25
b
f,
, BW
DQP
[71:0]
c
g
. During write
controls DQ
is controlled
Page 9 of 38
f
and DQP
a
c
–DQ
, and
[18:0]
f,
2
1
1
h
c