CY7C1470V25_12 CYPRESS [Cypress Semiconductor], CY7C1470V25_12 Datasheet - Page 27

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CY7C1470V25_12

Manufacturer Part Number
CY7C1470V25_12
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Switching Characteristics
Over the Operating Range
Document Number: 38-05290 Rev. *O
Notes
Parameter
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
23. Timing reference is 1.25 V when V
24. Test conditions shown in (a) of
25. This part has a voltage regulator internally; t
26. t
27. At any given voltage and temperature, t
28. This parameter is sampled and not 100% tested.
MAX
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
CHZ
[25]
, t
CLZ
, t
[23, 24]
EOLZ
, and t
V
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to Output low Z
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BW
ADV/LD set-up before CLK rise
Chip select set-up
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW
ADV/LD hold after CLK rise
Chip select hold after CLK rise
CC
EOHZ
(typical) to the first access read or write
are specified with AC test conditions shown in (b) of
x
x
Figure 4 on page 26
set-up before CLK rise
hold after CLK rise
DDQ
[26, 27, 28]
= 2.5 V and 0.9 V when V
EOHZ
[26, 27, 28]
power
is less than t
Description
is the time power needs to be supplied above V
unless otherwise noted.
[26, 27, 28]
[26, 27, 28]
EOLZ
and t
DDQ
CHZ
= 1.8 V.
is less than t
Figure 4 on page
CLZ
to eliminate bus contention between SRAMs when sharing the same data
DD(minimum)
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
26. Transition is measured ± 200 mV from steady-state voltage.
-200
initially, before a read or write operation can be initiated.
Max
200
3.0
3.0
3.0
3.0
Min
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
CY7C1470V25
CY7C1472V25
CY7C1474V25
-167
Max
167
3.4
3.4
3.4
3.4
Page 27 of 38
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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