CY7C1470V25_12 CYPRESS [Cypress Semiconductor], CY7C1470V25_12 Datasheet

CY7C1470V25_12

Manufacturer Part Number

CY7C1470V25_12

Description

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1470V25_12.pdf (38 pages)

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72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL

Features

■

Selection Guide

Cypress Semiconductor Corporation

Document Number: 38-05290 Rev. *O

Maximum access time

Maximum operating current

Maximum CMOS standby current

Pin-compatible and functionally equivalent to ZBT™

Supports 200-MHz bus operations with zero wait states

❐

Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

Fully registered (inputs and outputs) for pipelined operation

Byte write capability

Single 2.5 V power supply

2.5 V/1.8 V I/O supply (V

Fast clock-to-output times

❐

Clock enable (CEN) pin to suspend operation

Synchronous self-timed writes

CY7C1470V25 available in JEDEC-standard Pb-free 100-pin

TQFP, Pb-free and non Pb-free 165-ball FBGA package.

CY7C1472V25 available in JEDEC-standard Pb-free 100-pin

TQFP. CY7C1474V25 available in Pb-free and non Pb-free

209-ball FBGA package

IEEE 1149.1 JTAG boundary scan compatible

Burst capability – linear or interleaved burst order

“ZZ” sleep mode option and stop clock option

Available speed grades are 200 and 167 MHz

3.0 ns (for 200-MHz device)

Architecture

DDQ

)

•

Description

Pipelined SRAM with NoBL™ Architecture

198 Champion Court

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,

2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL logic, respectively. They are

designed to support unlimited true back-to-back read/write

operations

CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped

with the advanced (NoBL) logic required to enable consecutive

read/write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of data

in systems that require frequent write/read transitions. The

CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible

and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the Byte Write Selects

(BW

and BW

input. All writes are conducted with on-chip synchronous

self-timed write circuitry.

Three synchronous chip enables (CE

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated during

the data portion of a write sequence.

–BW

•

–BW

San Jose

for CY7C1474V25, BW

for CY7C1472V25) and a write enable (WE)

with

CA 95134-1709

200 MHz

450

120

wait

3.0

–BW

CY7C1470V25

CY7C1472V25

CY7C1474V25

, CE

Revised June 6, 2012

•

for CY7C1470V25

167 MHz

states.

, CE

400

120

3.4

408-943-2600

) and an

Unit

The

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