CY7C1470V25_12 CYPRESS [Cypress Semiconductor], CY7C1470V25_12 Datasheet - Page 11

• Manufacturer Part Number: CY7C1470V25_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

(DQ
DQ
CY7C1472V25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
DQ
CY7C1472V25) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BW
and
CY7C1470V25/CY7C1472V25/CY7C1474V25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
DQ
CY7C1472V25) inputs. Doing so will tri-state the output drivers.
As
(DQ
DQ
CY7C1472V25) are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in
Accesses on page
ZZ Mode Electrical Characteristics
Document Number: 38-05290 Rev. *O
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
a,b,c,d
a,b,c,d
a,b,c,d
a,b,c,d
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
remain
a
BW
/DQP
/DQP
/DQP
/DQP
a,b
a,b,c,d
a,b,c,d
a,b,c,d
safety
a,b,c,d
unaltered.
/DQP
/DQP
/DQP
/DQP
for CY7C1474V25, BW
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
for
10. When ADV/LD is driven HIGH on the
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
for CY7C1470V25 and DQ
for CY7C1470V25 and DQ
for CY7C1470V25 and DQ
for CY7C1470V25 & DQ
precaution,
CY7C1472V25)
Description
A
synchronous
for
for
for
for
a,b,c,d
DQ
for CY7C1470V25
self-timed
signals.
CY7C1474V25,
CY7C1474V25,
CY7C1474V25,
CY7C1474V25,
a,b
a,b
a,b
a,b
and
ZZ  V
ZZ V
This parameter is sampled
This parameter is sampled
Single Write
ZZ  0.2 V
/DQP
/DQP
/DQP
/DQP
a,b
a,b
a,b
a,b
DD
DD
DQP
write
The
 0.2 V
for
for
for
for
 0.2 V
Test Conditions
subsequent clock rise, the chip enables (CE
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
CY7C1470V25 and BW
driven in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or V
Address
Address
A1:A0
A1:A0
First
First
00
01
10
11
00
01
10
11
3
, must remain inactive for the duration of t
Address
Address
Second
Second
A1:A0
A1:A0
a,b,c,d,e,f,g,h
01
10
11
00
01
00
11
10
DD
a,b
)
for CY7C1472V25) inputs must be
for CY7C1474V25, BW
Address
Address
2t
A1:A0
A1:A0
Min
Third
Third
CYC
–
–
–
0
10
11
00
01
10
11
00
01
CY7C1470V25
CY7C1472V25
CY7C1474V25
1
2t
2t
, CE
Max
120
CYC
CYC
Address
Address
–
–
ZZREC
Fourth
Fourth
Page 11 of 38
A1:A0
A1:A0
2
11
00
01
10
11
10
01
00
, and CE
a,b,c,d
after the
1
Unit
mA
, CE
ns
ns
ns
ns
for
3
2
)
,