CY7C1470V25_12 CYPRESS [Cypress Semiconductor], CY7C1470V25_12 Datasheet - Page 12

• Manufacturer Part Number: CY7C1470V25_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Truth Table
The truth table for CY7C1470V25/CY7C1472V25/CY7C1474V25 follows.
Document Number: 38-05290 Rev. *O
Notes
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BW
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ
that the desired byte write selects are asserted, see Write Cycle Description table for details.
inactive or when the device is deselected, and DQ
Operation
[a:d]
. See Write Cycle Description table for details.
s
= data when OE is active.
Address Used CE ZZ ADV/LD WE BW
External
External
External
Current
None
None
None
None
Next
Next
Next
Next
H
X
L
X
L
X
L
X
L
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
[1, 2, 3, 4, 5, 6, 7]
x
= L signifies at least one byte write select is active, BW
H
H
H
H
H
X
X
L
L
L
L
L
X
X
H
X
H
X
X
X
X
X
L
L
X
X
X
X
X
X
H
H
X
X
L
L
x
OE CEN CLK
H
H
X
X
X
X
X
X
X
X
L
L
s
and DQP
H
X
L
L
L
L
L
L
L
L
L
L
CY7C1470V25
CY7C1472V25
CY7C1474V25
[a:d]
L–H
L–H
L–H Data out (Q)
L–H Data out (Q)
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
= tri-state when OE is
Data in (D)
Data in (D)
Page 12 of 38
x
= valid signifies
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
DQ
–