PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 58

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PI7C21P100NH

Manufacturer Part Number
PI7C21P100NH
Description
2-PORT PCI-X BRIDGE
Manufacturer
PERICOM [Pericom Semiconductor Corporation]
Datasheet

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8.1.48
8.1.49
8.1.50
8.1.51
8.1.52
OPAQUE MEMORY BASE REGISTER – OFFSET 74h
OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER – OFFSET 78h
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET
7Ch
PCI-X CAPABILITY ID REGISTER – OFFSET 80h
BIT
15:4
3:0
BIT
31:20
19:16
BIT
31:0
BIT
31:0
BIT
7:0
FUNCTION
Opaque Memory Base
Address
Address Select
FUNCTION
Opaque Memory Limit
Address
Address Select
FUNCTION
Opaque Memory Base
Upper 32-bit Register
FUNCTION
Opaque Memory Base
Upper 32-bit Register
FUNCTION
PCI-X Capability ID
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RO
RW
RO
RW
RW
RO
Page 58 of 77
DESCRIPTION
Opaque Memory Base Address
Address bits[31:20] of the opaque memory base address in
conjunction with the opaque memory base upper 32-bit register and
opaque memory limit address. In this range, memory transactions are
not accepted by PI7C21P100 on both primary and secondary
interfaces.
Reset to 000h
Address Select
Returns 0001 when read to indicate 64-bit addressing.
DESCRIPTION
Opaque Memory Limit Address
Address bits[31:20] of the opaque memory limit address in
conjunction with the opaque memory limit upper 32-bit register and
opaque memory base address. In this range, memory transactions are
not accepted by PI7C21P100 on both primary and secondary
interfaces.
Reset to FFFh
Address Select
Returns 0001 when read to indicate 64-bit addressing.
DESCRIPTION
Opaque Memory Base Upper 32-bit Register
Address bits[63:32] of the opaque memory base address. In this
range, memory transactions are not accepted by PI7C21P100 on both
primary and secondary interfaces.
Reset to FFFF FFFFh
DESCRIPTION
Opaque Memory Base Upper 32-bit Register
Address bits[63:32] of the opaque memory limit address. In this
range, memory transactions are not accepted by PI7C21P100 on both
primary and secondary interfaces.
Reset to FFFF FFFFh
DESCRIPTION
PCI-X Capability ID
Returns 07h when read to indicate that this register set of the
Capabilities List is a PCI-X register set.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100

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