PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 55

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.42
SERR# DISABLE REGISTER – OFFSET 5Ch
BIT
2
1
0
BIT
7:5
4
3
2
1
0
FUNCTION
Arbiter Priority 2
Arbiter Priority 1
Arbiter Priority 0
FUNCTION
RESERVED
PERR# on Posted
Writes SERR# Disable
Primary Discard Timer
SERR# Disable
Secondary Discard
Timer SERR# Disable
Primary Retry Count
SERR# Disable
Secondary Retry Count
SERR# Disable
TYPE
RW
RW
RW
TYPE
RO
RW
RW
RW
RW
RW
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DESCRIPTION
Arbiter Priority 2
0: Low priority request to master 2
1: High priority request to master 2
Reset to 0
Arbiter Priority 1
0: Low priority request to master 1
1: High priority request to master 1
Reset to 0
Arbiter Priority 0
0: Low priority request to internal bridge
1: High priority request to internal bridge
Reset to 1
DESCRIPTION
Reserved. Returns 000 when read.
PERR# on Posted Writes SERR# Disable
0: Assert SERR# and set bit[30] offset 04h of the status register if
bit[8] offset 04h in the command register is set. Discard the delayed
transaction.
1: Disable the assertion of SERR#.
Reset to 0
Primary Discard Timer SERR# Disable
0: Assert SERR# and update bit[30] offset 04h of the status register
if the primary discard timer expires and bit[8] offset 04h in the
command register is set and bit[27] offset 3Ch in the control register
is set. Discard the delayed transaction and set bit[3] offset 6Ch of the
retry and timer status register.
1: Disable the assertion of SERR# if the primary discard timer
expires. Discard the delayed transaction and set bit[3] offset 6Ch of
the retry and timer status register.
Reset to 0
Secondary Discard Timer SERR# Disable
0: Assert SERR# and update bit[30] offset 04h of the status register
if the secondary discard timer expires and bit[8] offset 04h in the
command register is set and bit[27] offset 3Ch in the control register
is set. Discard the delayed transaction and set bit[3] offset 6Ch of the
retry and timer status register.
1: Disable the assertion of SERR# if the primary discard timer
expires. Discard the delayed transaction and set bit[3] offset 6Ch of
the retry and timer status register.
Reset to 0
Primary Retry Count SERR# Disable
0: Assert SERR# and update bit[30] offset 04h of the status register
if the primary retry counter expires and bit[8] offset 04h in the
command register is set. Discard the transaction and set bit[1] offset
6Ch of the retry and timer status register.
1: Disable the assertion of SERR# if the primary retry counter
expires. Discard the transaction and set bit[1] offset 6Ch of the retry
and timer status register.
Reset to 0
Secondary Retry Count SERR# Disable
0: Assert SERR# and update bit[30] offset 04h of the status register
if the secondary retry counter expires and bit[8] offset 04h in the
command register is set. Discard the transaction and set bit[0] offset
6Ch of the retry and timer status register.
1: Disable the assertion of SERR# if the primary retry counter
expires. Discard the transaction and set bit[0] offset 6Ch of the retry
and timer status register.
Reset to 0
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100