PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 37

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

7.1
7.2
PRIMARY INTERFACE RESET
When P_RST# is asserted, the following events occur:
PI7C21P100 is not accessible during P_RST#. After P_RST# is deasserted in PCI-X mode,
PI7C21P100 remains inaccessible for 100us to enable the internal PLL to lock to its target
frequency. In conventional PCI mode, PI7C21P100 is held in reset 7 PCI clocks after the
deassertion of P_RST#.
SECONDARY INTERFACE RESET
PI7C21P100 is responsible for driving the secondary bus reset signals, S_RST#. PI721P100
asserts S_RST# when any of the following conditions are met:
Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted
and does not de-assert until P_RST# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RST# remains
asserted until a configuration write operation clears the secondary reset bit.
Several things must occur at or prior to the de-assertion of S_RST#. Once P_RST# is
de-asserted or the secondary bus reset bit is changed from 1 to 0, PI7C21P100 will wait for
the S_CLK_STABLE signal to be asserted before proceeding. S_CLK must be stable at a
frequency within the bus capability limits prior to the assertion of S_CLK_STABLE. Since
the PCI Local Bus Specification requires that the bus clock be stable for at least 100us prior to
the de-assertion of the bus reset, S_CLK_STABLE serves as a gate to a timer that ensures that
this requirement is met. During this time delay period, the secondary bus mode and frequency
is determined through the programmable pull-up circuit. This process may include up to 80us
for the capacitive load on S_PCIXCAP to be charged. By the time the 100us timer expires,
the bus mode and frequency will have been determined. The S_RST# signal is then
de-asserted a minimum of ten secondary bus PCI clock cycles later.
When the secondary bus is operating in PCI-X mode, an internal PLL is used to source the
clock tree for the secondary clock domain inside PI7C21P100. The appropriate range and
tuning bits for the PLL are set once the mode and frequency are determined, and an internal
PLL reset signal is deactivated to allow the PLL to begin locking to the S_CLK input
frequency. The PLL requires an allowance of 100us to accomplish this frequency lock. An
internal reset is held on the logic in the secondary clock domain until this time period has
elapsed. While the internal reset is active, PI7C21P100 will not respond to any secondary bus
transactions. When the secondary bus is operating in PCI mode, the internal PLL for the
secondary interface is not used. The internal PLL reset remains activated, keeping the PLL in
the bypass mode, and the internal logic reset is held for 5 additional secondary PCI clock
cycles.
PI7C21P100 immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-
stated.
PI7C21P100 performs a chip reset.
Registers that have default values are reset.
Page 37 of 77
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100