PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 36

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

6.3.3
6.3.4
7
Table 6-2 DRIVER IMPEDANCE SELECTION
CLOCK STABILITY
To comply with PCI and PCI-X architecture specifications, the bus clock must be stable and
running at the designated frequency for at least 100us after deassertion of the bus reset.
S_CLK_STABLE is used to determine and detect when S_CLK has become stable. During a
bus reset, PI7C21P100 will wait for the assertion of S_CLK_STABLE before determining the
mode and frequency. PI7C21P100 is expecting no more than one transition on the
S_CLK_STABLE input from the “not stable” to the “stable” state. S_CLK_STABLE input
may be tied HIGH if the secondary clock input is known to be always stable prior to the
deassertion of the primary bus reset signal or the secondary bus reset bit of the bridge control
register. Examples of sources for S_CLK_STABLE are lock indicators on circuits that
employ PLL’s or “power good” indicators.
DRIVER IMPEDANCE SELECTION
The output drivers on PI7C21P100 are capable of two different output impedances, 40 ohm
output impedance and a 20 ohm. The output impedance for the primary and secondary
interfaces is separately controlled. PI7C21P100 selects a default impedance value at the
deassertion of the bus reset based on the bus mode and frequency. If a bus is configured to be
in PCI-X 133 mode, it is assumed that the bus will have fewer devices and have a higher
impedance. In this case, the drivers utilize the 40 ohm output impedance mode. The 20 ohm
output impedance mode is utilized for all other PCI-X and all PCI configurations, assuming
that the bus is more heavily loaded and has lower impedance. Some applications do not
follow these assumptions so two control signals are provided; P_DRVR for the primary and
S_DRVR for the secondary. When these inputs are pulled HIGH, PI7C21P100 will change
the output impedance of the drivers on their respective interfaces to the opposite state than
was assumed by default, as shown in Table 6-2. The driver mode may not be changed
dynamically, but can be changed during each bus reset.
RESET
The primary and secondary interface each have their own asynchronous reset signal used at
power-on and at other times to put PI7C21P100 into a known state. The reset signal on the
primary (P_RST#) is an input pin, while the reset signal on the secondary (S_RST#) is an
output pin driven by PI7C21P100.
Primary Bus
Mode
Conventional
PCI
PCI-X 66
PCI-X 100
PCI-X 133
Default Driver
Mode
(P_DRVR=0)
20 ohm
20 ohm
20 ohm
20 ohm
Driver Mode if
(P_DRVR=1)
Page 36 of 77
40 ohm
40 ohm
40 ohm
20 ohm
Secondary Bus
Mode
Conventional
PCI
PCI-X 66
PCI-X 100
PCI-X 133
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
Default Driver
Mode
(S_DRVR=0)
2-PORT PCI-X BRIDGE
20 ohm
20 ohm
20 ohm
40 ohm
PI7C21P100
Driver Mode if
(S_DRVR=1)
40 ohm
40 ohm
40 ohm
20 ohm