PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 16

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

3.2.6
STRAPPING PINS AND MISCELLANEOUS SIGNALS
Name
S__ARB#
S_SEL100
S_PCIXCAP
S_PCIXCAP_PU
S_DRVR
P_DRVR
S_CLK_STABLE
S_IDSEL
Pin #
T21
V3
R23
AA1
AC7
E2
W3
AA22
Page 16 of 77
Type
ID
ID
I
I
I
I
I
I
Description
Internal Arbiter Enable: This pin is used by
PI7C21P100 to determine whether the secondary bus
uses the internal arbiter or external arbiter.
0: Enable the internal arbiter
1: Disable the internal arbiter and use an external arbiter
Secondary Bus Maximum Frequency: This pin is used
to determine the maximum frequency on the secondary
bus when in PCI-X mode. In PCI mode, the pin has no
function and should not be left floating.
0: Set secondary interface to 133MHz
1: Set secondary interface to 100MHz
Secondary Bus PCI-X Capable: This pin is used with
S_SEL100 to determine the frequency and mode for the
secondary bus. There are three conditions for this pin
determining the capability of the secondary bus:
Ground: Not capable of PCI-X mode
Pull-down: PCI-X 66MHz
Not connected: PCI-X 133MHz
S_PCIXCAP Pull-up Driver: This pin is used with
S_PCIXAP as part of a programmable pull-up circuit to
determine the state of S_PCIXCAP. A 1kohm resistor
must be placed between this pin and S_PCIXCAP.
Secondary Driver Mode: This pin controls the output
impedance of the secondary drivers to account for the
number of loads on the secondary bus.
0: default impedance
1: select alternate impedance
See Table 6-2 for impedance values.
Primary Driver Mode Control: Controls the output
impedance of the primary bus drivers to account for the
number of loads on the primary bus.
0: Default impedance
1: Select alternate impedance
S_CLK Input Stable: Determines when the S_CLK is
stable to resolve when S_RST# can by de-asserted.
0: S_CLK is not stable
1: S_CLK is stable
Initialization Device Select: S_IDSEL is used as a chip
select during configuration reads and writes on the
secondary bus. Applications that do not require access
to PI7C21P100’s configuration registers from the
secondary side should pull this pin LOW.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100