PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 12

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

3.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION
Name
P_AD[63:32]
P_CBE[7:4]#
P_PAR64
P_REQ64#
P_ACK64#
Pin #
B11, D10, C10, A4,
B10, C9, B9, A3, B8,
B3, C7, B7, D6, B6,
B5, C2, D2, F4, E3,
F3, B1, F2, G3, H3,
H2, E1, J3, G1, H1,
J2, J1, L1
A7, B12, C11, A5
A9
C12
A2
Page 12 of 77
Type
STS
STS
TS
TS
TS
Description
Primary Upper 32-bit Address / Data: Multiplexed
address and data bus providing an additional 32 bits to
the primary. When a dual address command is used and
P_REQ64# is asserted, the initiator drives the upper 32
bits of the 64-bit address. Otherwise, these bits are
undefined and driven to valid logic levels. During the
data phase of a transaction, the initiator drives the upper
32 bits of the 64-bit write data, or the target drives the
upper 32 bits of the 64-bit read data, when P_REQ64#
and P_ACK64# are both asserted. Otherwise, these bits
are pulled up to a valid logic level through external
resistors.
Primary Upper 32-bit Command/Byte Enables:
Multiplexed command field and byte enable field.
During address phase, when the dual address command
is used and P_REQ64# is asserted, the initiator drives the
transaction type on these pins. Otherwise, these bits are
undefined, and the initiator drives a valid logic level onto
the pins. For read and write transactions, the initiator
drives these bits for the P_AD[63:32] data bits when
P_REQ64# and P_ACK64# are both asserted. When not
driven, these bits are pulled up to a valid logic level
through external resistors.
Primary Upper 32-bit Parity: P_PAR64 carries the
even parity of P_AD[63:32] and P_CBE[7:4] for both
address and data phases. P_PAR64 is driven by the
initiator and is valid 1 cycle after the first address phase
when a dual address command is used and P_REQ64# is
asserted. P_PAR64 is valid 1 clock cycle after the
second address phase of a dual address transaction when
P_REQ64# is asserted. P_PAR64 is valid 1 cycle after
valid data is driven when both P_REQ64# and
P_ACK64# are asserted for that data phase. P_PAR64 is
driven by the device driving read or write data 1 cycle
after the P_AD lines are driven. P_PAR64 is tri-stated 1
cycle after the P_AD lines are tri-stated. Devices receive
data sample P_PAR64 as an input to check for possible
parity errors during 64-bit transactions. When not driven,
P_PAR64 is pulled up to a valid logic level through
external resistors.
Primary 64-bit Transfer Request: P_REQ64# is
asserted by the initiator to indicate that the initiator is
requesting a 64-bit data transfer. P_REQ64# has the
same timing as P_FRAME#. When P_REQ64# is
asserted LOW during reset, a 64-bit data path is
supported. When P_REQ64# is HIGH during reset,
PI7C21P100 drives P_AD[63:32], P_CBE[7:4], and
P_PAR64 to valid logic levels. When deasserting,
P_REQ64# is driven HIGH for 1 cycle and then
sustained by an external pull-up resistor.
Primary 64-bit Transfer Acknowledge: P_ACK64# is
asserted by the target only when P_REQ64# is asserted
by the initiator to indicate the target’s ability to transfer
data using 64 bits. P_ACK64# has the same timing as
P_DEVSEL#. When deasserting, P_ACK64# is driven
HIGH for 1 cycle and then is sustained by an external
pull-up resistor.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100