PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 34

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

6
6.1
6.2
6.3
6.3.1
CLOCKS
This chapter provides information about the clocks.
PRIMARY AND SECONDARY CLOCK INPUTS
The primary and secondary interface on PI7C21P100 each has its own clock input pin.
P_CLK is the clock input for the primary and S_CLK is the input for the secondary (S_CLK
also controls the internal arbiter). The two clocks are independent of each other and may be
run synchronously or asynchronously to each other at any value supported by the PCI or PCI-
X specifications. Each interface utilizes a separate internal PLL (phase-locked loop) circuit
when running in PCI-X mode. In PCI mode, the PLL’s are bypassed, allowing for any clock
frequency from 0 to 66MHz. If the primary is running at 133MHz in PCI-X mode, then the
secondary is limited to a minimum frequency of 33MHz in conventional PCI mode. To run
the secondary slower, the primary frequency needs to be reduced so that the ratio does not
exceed 4:1.
CLOCK JITTER
PI7C21P100 tolerates a maximum of +/- 250ps of short term and long term jitter on the clock
inputs. Short term jitter is defined as the relationship between one clock edge to the next
subsequent clock edge for one clock cycle, and long term jitter is the same relationship over
many clock cycles.
MODE AND CLOCK FREQUENCY DETERMINATION
PRIMARY BUS
PI7C21P100 does not have I/O pins for the M66EN or PCIXCAP signals on the primary bus.
PI7C21P100 adjusts its internal configuration based on the initialization pattern it detects on
P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#. If the internal PLL is
being used (the bus is configured in the PCI-X mode), a maximum of 100μs from the rising
edge of P_RST# is required to lock the PLL to the frequency of the clock supplied on the
P_CLK input.
Pass
Delayed Read Completion
Delayed Write Completion
1. If the relaxed ordering bit is set in PCI-X to PCI-X mode, or the enable relaxed ordering bit in the primary and/or
secondary data buffering control registers is set in any other mode, read completions can pass memory writes.
2. Split Read Completions with the same sequence ID must remain in address order.
Memory
Write
No
No
1
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Split Read
Request
Yes
Yes
Split Write
Request
Yes
Yes
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
Split Read
Completion
Yes
Yes
2
PI7C21P100
Split Write
Completion
Yes
No