MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 68

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

ZQ Calibration
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Whenever the DLL RESET function is initiated, CK/CK# must be held stable for 512
clock cycles before a READ command can be issued. This is to allow time for the inter-
nal clock to be synchronized with the external clock. Failing to wait for synchronization
to occur may cause output timing specifications, such as
The ZQ CALIBRATION mode register command is used to calibrate the DRAM output
drivers (R
dedicated 240Ω (±1%) external resistor is connected from the DRAM’s RZQ ball to V
Bit MR1[6] selects between ZQ calibration long (ZQCL) and ZQ calibration short
(ZQCS), each of which are described in detail below. When bit MR1[7] is set HIGH, it
enables the calibration sequence. Upon completion of the ZQ calibration sequence,
MR1[7] automatically resets LOW.
The RLDRAM 3 needs a longer time to calibrate R
and a relatively shorter time to perform periodic calibrations. An example of ZQ calibra-
tion timing is shown below.
All banks must have
to the DRAM. No other activities (other than loading another ZQCL or ZQCS mode reg-
ister setting may be issued to another DRAM) can be performed on the DRAM channel
by the controller for the duration of
channel helps accurately calibrate R
the DRAM will disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION mode register settings can be loaded in parallel to DLL reset and
locking time.
In systems that share the ZQ resistor between devices, the controller must not allow
overlap of
ON
t
ZQinit,
) and ODT values (R
t
ZQoper, or
t
RC met before ZQCL or ZQCS mode register settings can be issued
68
t
ZQcs between devices.
TT
) over process, voltage, and temperature, provided a
t
ON
ZQinit or
and ODT. After DRAM calibration is achieved,
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
ZQoper. The quiet time on the DRAM
ON
576Mb: x18, x36 RLDRAM 3
and ODT at power-up initialization
Mode Register 1 (MR1)
t
CKQK, to be invalid .
© 2011 Micron Technology, Inc. All rights reserved.
SSQ
.