MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 5

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

List of Figures
Figure 1: 576Mb RLDRAM
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10
Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11
Figure 5: 168-Ball FBGA ................................................................................................................................. 16
Figure 6: Single-Ended Input Signal ............................................................................................................... 23
Figure 7: Overshoot ....................................................................................................................................... 24
Figure 8: Undershoot .................................................................................................................................... 24
Figure 9: V
Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26
Figure 11: Definition of Differential AC Swing and
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29
Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30
Figure 15: Output Driver ................................................................................................................................ 33
Figure 16: DQ Output Signal .......................................................................................................................... 38
Figure 17: Differential Output Signal .............................................................................................................. 39
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41
Figure 21: Example Temperature Test Point Location ...................................................................................... 49
Figure 22: Nominal Slew Rate and
Figure 23: Nominal Slew Rate for
Figure 24: Tangent Line for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate and
Figure 27: Nominal Slew Rate for
Figure 28: Tangent Line for
Figure 29: Tangent Line for
Figure 30: MRS Command Protocol ............................................................................................................... 63
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 64
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 67
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 69
Figure 34: Read Burst Lengths ........................................................................................................................ 71
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 72
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 73
Figure 37: WRITE Command ......................................................................................................................... 74
Figure 38: READ Command ........................................................................................................................... 76
Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 77
Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 78
Figure 41: Power-Up/Initialization Sequence ................................................................................................. 80
Figure 42: WRITE Burst ................................................................................................................................. 82
Figure 43: Consecutive WRITE Bursts ............................................................................................................. 83
Figure 44: WRITE-to-READ ............................................................................................................................ 83
Figure 45: WRITE - DM Operation .................................................................................................................. 84
Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 85
Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 85
Figure 48: Basic READ Burst .......................................................................................................................... 86
Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 87
Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 87
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
IX
for Differential Signals ................................................................................................................ 25
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t
t
t
t
3 Part Numbers ..................................................................................................... 2
IS (Command and Address - Clock) ...................................................................... 54
IH (Command and Address - Clock) ..................................................................... 55
DS (DQ - Strobe) ................................................................................................. 60
DH (DQ - Strobe) ................................................................................................ 61
t
t
IH (Command and Address - Clock) ............................................................ 53
DH (DQ - Strobe) ........................................................................................ 59
t
t
VAC for
VAC for
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t
IS (Command and Address - Clock) ............................................... 52
DS (DQ - Strobe) .......................................................................... 58
t
DVAC ................................................................................ 26
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576Mb: x18, x36 RLDRAM 3
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