MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 67

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Mode Register 1 (MR1)
Figure 32: MR1 Definition for Non-Multiplexed Address Mode
Output Drive Impedance
DQ On-Die Termination (ODT)
DLL Reset
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
Notes:
The RLDRAM 3 uses programmable impedance output buffers, which enable the user
to match the driver impedance to the system. MR1[0] and MR1[1] are used to select 40Ω
or 60Ω output impedance, but the device powers up with an output impedance of 40Ω.
The drivers have symmetrical output impedance. To calibrate the impedance a 240Ω
±1% external precision resistor (RZQ) is connected between the ZQ ball and V
The output impedance is calibrated during initialization through the ZQCL mode regis-
ter setting. Subsequent periodic calibrations (ZQCS) may be performed to compensate
for shifts in output impedance due to changes in temperature and voltage. More de-
tailed information on calibration can be found in the ZQ Calibration section.
MR1[4:2] are used to select the value of the on-die termination (ODT) for the DQ, DKx
and DM balls. When enabled, ODT terminates these balls to V
device supports 40Ω, 60Ω, or 120Ω ODT. The ODT function is dynamically switched off
when a DQ begins to drive after a READ command has been issued. Similarly, ODT is
designed to switch on at the DQs after the RLDRAM has issued the last piece of data.
The DM and DKx balls are always terminated after ODT is enabled.
Programming MR1[5] to 1 activates the DLL RESET function. MR1[5] is self-clearing,
meaning it returns to a value of 0 after the DLL RESET function has been initiated.
M8
0
1
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
2. BL8 not available in x36.
Bank Address Control
M10
the MRS command.
0
0
1
1
AREF P rotocol
Multibank
M9
0
1
0
1
BA3
0
21
1
Burst Length
BA2
20
0
Reserved
1
BA1
19
MRS
2
4
8
18
BA0
Reserved
A17 ... A11
17-11
M7
0
1
ZQ Calibration Enable
10
Disabled - Default
A10
BL
M6
0
1
9
A9
Enable
ZQ Calibration Selection
Ref
Short ZQ Calibration
Long ZQ Calibration
8
67
A8
ZQe
M5
7
0
1
A7
ZQ
6
A6
DLL Reset
DLL
Yes
5
No
A5
4
A4
ODT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
3
A3
M4
2
0
0
0
0
1
1
1
1
A2
Drive
M3
1
A1
0
0
1
1
0
0
1
1
0
M2
A0
0
1
0
1
0
1
0
1
576Mb: x18, x36 RLDRAM 3
Address Bus
Mode Register (Mx)
RZQ/2 (120W)
RZQ/6 (40W)
RZQ/4 (60W)
Reserved
Reserved
Reserved
Reserved
ODT
Off
Mode Register 1 (MR1)
M1
0
0
1
1
DDQ
© 2011 Micron Technology, Inc. All rights reserved.
M0
0
1
0
1
/2. The RLDRAM 3
Output Drive
RZQ/6 (40W)
RZQ/4 (60W)
Reserved
Reserved
SSQ
.