MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 65

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

t
Data Latency
DLL Enable/Disable
Address Multiplexing
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
RC
Bits MR0[3:0] select the number of clock cycles required to satisfy the
After a READ, WRITE, or AREF command is issued to a bank, a subsequent READ,
WRITE, or AREF cannot be issued to the same bank until
correct value (
Table 38:
The data latency register uses MR0[7:4] to set both the READ and WRITE latency (RL
and WL). The valid operating frequencies for each data latency register setting can be
found in Table 27 (page 43).
Through the programming of MR0[8], the DLL can be enabled or disabled.
The DLL must be enabled for normal operation. The DLL must be enabled during the
initialization routine and upon returning to normal operation after having been disa-
bled for the purpose of debugging or evaluation. To operate the RLDRAM with the DLL
disabled, the
DLL should always be followed by resetting the DLL using the appropriate MR1 com-
mand.
Although the RLDRAM has the ability to operate similar to an SRAM interface by ac-
cepting the entire address in one clock (non-multiplexed, or broadside addressing),
MR0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a tra-
ditional DRAM. In multiplexed address mode, the address is provided to the RLDRAM
in two parts that are latched into the memory with two consecutive rising edges of CK.
Parameter
RL = 3; WL = 4
RL = 4; WL = 5
RL = 5; WL = 6
RL = 6; WL = 7
RL = 7; WL = 8
RL = 8; WL = 9
RL = 9; WL = 10
RL = 10; WL = 11
RL = 11; WL = 12
RL = 12; WL = 13
RL = 13; WL = 14
RL = 14; WL = 15
RL = 15; WL = 16
RL = 16; WL = 17
t
RC_MRS MR0[3:0] values
t
RC MRS setting must equal the read latency (RL) setting. Enabling the
t
RC_MRS) to program into MR0[3:0] is shown in the table below.
-093E
2
2
3
4
4
5
5
6
6
7
7
8
8
9
65
-093
10
10
11
2
3
4
4
4
6
6
7
7
8
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Reserved
Reserved
-107E
2
3
3
4
4
5
5
6
6
7
7
8
576Mb: x18, x36 RLDRAM 3
Reserved
Reserved
Mode Register 0 (MR0)
-107
t
RC has been satisfied. The
10
3
3
4
4
5
6
6
7
7
8
8
© 2011 Micron Technology, Inc. All rights reserved.
Reserved
Reserved
Reserved
Reserved
-125E
t
RC specifications.
3
3
4
4
5
6
6
7
7
8
Reserved
-125
10
10
3
3
4
4
5
6
6
7
7
8
9